Oxide-Nitride Passivation Etch in 28nm: Physics, Integration Mechanisms, and Failure Dynamics

Function in the Complete Flow

In the architecture of the 28nm Planar process flow, the contact border (CB) etch—frequently designated as the passivation opening etch or pad opening process—serves as the critical transition step between back end of line (BEOL) wafer fabrication and packaging assembly [P1, T2]. Prior to this process, the functional complementary metal-oxide-semiconductor (CMOS) integrated circuit components and multi-level copper interconnect networks are completely sealed beneath a composite dielectric passivation layer deposited across the wafer [P1, T1]. This final protective barrier consists of a dual-layer silicon dioxide and silicon nitride film stack designed to shield delicate underlying low-k interconnects against atmospheric moisture, ionic contamination, and mechanical stress during handling [P1, A2].

The fundamental role of the CB etch step is to selectively open discrete access ports—known as the CB etch chip bond window—through this top passivation stack directly down to the terminal metal bond pads [P1, A1]. By selectively carving out these openings while preserving the integrity of the surrounding moisture-barrier dielectric, this step defines the precise electrical interface for subsequent assembly schemes [P1, T2]. Whether the chip is destined for traditional wire bonding or direct advanced packaging via the 28nm Planar copper bump integration process flow, the quality of the pad opening integration dictates the electrical contact resistance, mechanical adhesion, and long-term joint reliability of the final product [P1, A1].

+-------------------------------------------------------------+
|               Patterned Photoresist Mask                    |
+-------------------------------------------------------------+
|     Silicon Nitride (SiN) Primary Passivation Cap           |
+-------------------------------------------------------------+
|     Silicon Dioxide (SiO2) Stress-Relief Buffer Layer       |
+-------------------------------------------------------------+
|   Top Metal Pad (Al Cap / Cu Landing Pad)  |  BEOL Oxide    |
+-------------------------------------------------------------+

Executing this selective dielectric etch requires balancing directional anisotropic erosion with extreme chemical selectivity toward the underlying metallic landing pad [P2, T1]. Under-etching leaves residual insulation over the landing pad, leading to open-circuit failures or high contact resistance during solder bump formation [P1]. Conversely, aggressive over-etching can cause severe pad sputtering, metal recessing, micro-trenching, or sidewall polymer redeposition, compromising the under-bump metallization (UBM) interface [P1, P3]. Thus, the passivation opening etch mechanism forms the physical bridge connecting nanoscale device manufacturing to millimeter-scale system packaging [P1, A1].

Upstream Input State

Entering this processing phase, the semiconductor wafer inherits a fully realized BEOL interconnect stack built over planar 28nm transistor architectures [T1, T2]. The incoming structural state features multi-level copper dual-damascene metallization lines embedded within low-density, low-k inter-level dielectrics [T1]. At the apex of this interconnect fabric rests the top metal layer—typically comprising a robust copper pad capped with an aluminum-copper alloy layer designed to withstand high mechanical impact during assembly (Engineering Practice).

Over this top metallization structure, the dual-layer passivation dielectric stack is blanket-deposited via plasma-enhanced chemical vapor deposition (PECVD) at elevated processing temperatures compatible with the thermal budget of the underlying BEOL metal layers [P1, T1]. The bottom component of this stack is a silicon dioxide (SiO2) buffer layer, which cushions the underlying metal from mechanical stress and mitigates coefficient of thermal expansion (CTE) mismatches [P1, A2]. Superimposed above the oxide buffer is a thicker, highly dense silicon nitride (SiN or Si3N4) layer [P1, T1]. This silicon nitride cap provides impermeable sealing against moisture ingress and mobile alkali ions [P1].

Incoming Wafer Topography and Masking Architecture:

[ Lithography Photoresist Pattern ]
              |
              v
+-------------------------------------------------------------+
|  Dense Silicon Nitride (SiN Cap) - Primary Barrier          |
+-------------------------------------------------------------+
|  Silicon Dioxide (SiO2 Buffer) - Stress Mitigation          |
+-------------------------------------------------------------+
|  Top Metal Pad (Al-Cu / Cu)   | Top BEOL Dielectric Layer   |
+-------------------------------------------------------------+

To prepare for the contact border etch, an organic bottom anti-reflective coating (BARC) followed by a thick photoresist layer is coated and lithographically patterned across the wafer [T2, A2]. The incoming wafer exhibits notable localized surface topography resulting from the underlying thick top metal pads, which creates non-uniform resist accumulation across pad edges [P3, A2]. Additionally, incoming PECVD films retain intrinsic mechanical stress—predominantly compressive in the silicon nitride layer—which must be accommodated during opening formation to avoid micro-fracturing along pad boundaries [A2]. The surface state of the top metal cap must also remain unoxidized and pristine beneath the oxide buffer prior to etching to ensure uniform landing [P1, P3].

Physical and Chemical Mechanisms

The oxide-nitride passivation etch is executed within a high-density plasma reactive ion etching (RIE) system operating under fluorocarbon-based gas chemistries [P2, T1]. The dual-layer composite stack demands a multi-phase etching mechanism that dynamically balances chemical radical reaction kinetics with physical ion-assisted momentum transfer [P2, T1].

Etch Plasma Dynamics inside RIE Chamber:

   Fluorocarbon Gas Mixture (C4F8/CF4 + O2 + Ar)
                        |
                        v  [Plasma Ionization]
        +-------------------------------+
        |  CFx+ Ions    |  F* Radicals  |
        +-------------------------------+
            |                 |
            v (Directional)   v (Chemical)
   Physical Sputtering    Surface Polymerization & Reaction
            \                 /
             v               v
   +------------------------------------+
   | Anisotropic Passivation Etch Front |
   +------------------------------------+

1 [P2]. Silicon Nitride Passivation Cap Etching

The initial phase of the dielectric etch targets the dense silicon nitride top layer [P1, T1]. Fluorocarbon source gases (such as octafluorocyclobutane or tetrafluoromethane mixed with argon and oxygen) dissociate within the high-density plasma to form reactive atomic fluorine radicals, fluorocarbon species, and energetic positive ions [P2, T1]. Chemical reaction kinetics drive the breakdown of the silicon nitride lattice through the breaking of Si–N bonds, producing volatile silicon tetrafluoride (SiF4) and gaseous nitrogen molecules that are continuously evacuated from the chamber [T1]. Energetic argon ions accelerated normal to the wafer surface by the plasma sheath bias provide directionality, removing passivation polymers from horizontal surfaces while leaving sidewalls protected [P2, T1].

2. Silicon Dioxide Buffer Layer Etching

As the etch front penetrates through the nitride layer and encounters the underlying silicon dioxide buffer, the dominant chemical mechanism shifts [P2, T1]. In fluorocarbon plasmas, silicon dioxide etching relies heavily on oxygen liberated directly from the breaking SiO2 crystal matrix [P2, T1]. The oxygen released from the oxide reacts with surface-adsorbed fluorocarbon polymer fragments to produce volatile carbon dioxide (CO2) and carbon monoxide (CO), maintaining a thin, steady-state polymer film at the etch interface [P2, T1]. This self-regulating fluorocarbon film promotes high directional anisotropy and allows fine control of the sidewall profile [P2].

3. Sidewall Taper Profile and Polymer Dynamics

Achieving an optimal contact border profile requires balancing polymer film deposition against ion-assisted polymer sputtering [P2]. Active radicals form a thin fluorocarbon protective film along the etching feature [P2]. Because vertical sidewalls receive minimal direct impact from normal-incidence ions, the fluorocarbon polymer accumulates along the upper profile corners, gradually reducing horizontal lateral erosion [P2]. This controlled polymer buildup produces a tapered sidewall profile rather than an absolute vertical cliff [P2]. Controlled sidewall tapering is crucial in 28nm pad opening integration: it prevents step-coverage voiding during subsequent metallization deposition while preventing excessive widening of the top critical dimension (CD) [P2, A1].

Passivation Opening Profile Dynamics:

     Ion Bombardment Direction (Normal to Wafer)
                    |||||||
                    vvvvvvv
         Photoresist Mask   Photoresist Mask
        +-----------------+ +-----------------+
        |                 | |                 |
        |  Polymer Layer  | |  Polymer Layer  |
        |  Accumulation   \ /  Accumulation   |
        +---\--------------+--------------/---+
             \  Tapered Dielectric Profile /
              \   (Controlled Slope)      /
               +-------------------------+
               |   Top Metal Landing Pad |
               +-------------------------+

4 [P2]. High-Selectivity Metal Landing and Stop Mechanism

The critical endpoint of the passivation opening etch mechanism occurs when the etch front reaches the top metal pad [P1, T2]. The fluorine-based plasma must cease downward etching immediately upon exposing the metallic pad surface [P1, T1]. When exposed to fluorocarbon plasma, metals such as aluminum or copper do not form volatile fluoride species under typical RIE operating temperatures (Engineering Practice). Instead, a thin, non-volatile metal-fluoride passivation layer forms on top of the metal pad, dramatically suppressing the etch rate [P2, T1]. This mechanism provides high dielectric-to-metal selectivity, preserving the physical thickness and electrical conductivity of the metal landing pad [P1, T2]. Optical emission spectroscopy (OES) tracks chemical radical emission signals in the plasma (monitoring species depletion or metal sputtering peaks) to pinpoint the exact interface transit and trigger the endpoint etch phase [T2].

5. Post-Etch Ashing and Residue Decontamination

Upon completion of the dry etch step, the wafer surface remains covered with fluorocarbon polymer residues, highly cross-linked photoresist remnants, and metal-fluoride surface complexes [P1, T1]. A downstream oxygen/nitrogen-based plasma ash step is executed to combust organic resist and polymeric residues [T1]. This is followed by a wet chemical clean utilizing specialized organic solvents or mild alkaline solutions designed to dissolve residual fluorocompounds without attacking or corroding the exposed aluminum/copper pad surface [P1, P3].

Etch Phase	Primary Chemical Species	Physical Process	Core Selectivity / Mechanism Goal
Nitride Etch	Fluorine radicals, CFx species [T1]	Ion-assisted Si–N bond cleavage [P2, T1]	Rapid Si3N4 breakdown with anisotropic control [P1, T1]
Oxide Etch	Fluorocarbon polymer radicals [P2]	Matrix oxygen release + CO/CO2 evacuation [P2, T1]	Steady polymer film equilibrium and profile taper control [P2]
Metal Stop	Fluorine ions, Inert carriers [P2, T1]	Surface metal-fluoride film formation [P2, T1]	High dielectric-to-metal selectivity to preserve pad integrity [P1, T2]
Residue Strip	Oxygen/Hydrogen plasma species [T1]	Surface oxidation of organics & wet polymer strip [P1, T1]	Corrosion-free removal of polymer residues [P1, P3]

Downstream Impact and Failure Propagation

Process variations or marginalities during the contact border etch directly affect subsequent back-end integration steps, packaging success, and ultimate product reliability [P1, A1]. Because this step exposes the underlying electrical network to the outside world, failure modes originating here propagate directly into package-level defects [P1, A2].

+-----------------------------------------------------------------+
|               Passivation Etch Marginality                      |
+-----------------------------------------------------------------+
               |                                   |
               v                                   v
   [ Incomplete Oxide Etch ]             [ Over-Etch / Metal Sputter ]
               |                                   |
               v                                   v
   - High Contact Resistance             - Metal Pad Micro-trenching
   - Electrical Open Circuit             - Fluorine-Driven Galvanic Corrosion
   - UBM Interfacial Delamination       - Package Stress Micro-cracks
               |                                   |
               +-----------------+-----------------+
                                 |
                                 v
                 [ Package & Reliability Failure ]

Contact Resistance Spikes and Open Circuits

If the CB etch rate decelerates due to excessive polymer accumulation or premature endpoint detection, a thin residual dielectric membrane can remain over the top metal pad [P1, P2]. During subsequent 28nm copper bump integration or wire bonding, this residual dielectric acts as an insulating barrier, causing severe contact resistance spikes or total open circuits [P1, A1]. In flip-chip architectures, non-uniform residual oxide across a die causes variable bump shear strength and localized electrical failure [P1, A1].

Sidewall Taper Aberrations and UBM Delamination

The sidewall profile of the CB etch chip bond window dictates the step coverage of barrier and seed layers deposited during subsequent under-bump metallization [P2, A1]. If the etch produces overly vertical or undercut sidewalls due to insufficient polymer protection, physical vapor deposition (PVD) sputtering of titanium/copper UBM seed layers cannot achieve continuous coverage over the steep step [P2, A1]. This leads to sub-micron voiding along the lower corners of the opening, acting as stress concentrators during thermal cycling and driving interfacial UBM delamination or solder joint cracking [P1, A1].

Metal Pad Micro-Trenching and Galvanic Corrosion

Excessive over-etching or unoptimized plasma bias energy can cause ion bombardment to punch through the surface metal-fluoride layer, sputtering the underlying metal pad [P1, P3]. This physical sputtering forms deep micro-trenches along the perimeter of the pad window [P2]. Furthermore, if fluorocarbon polymer species become embedded within the sputtered metal pad matrix and are inadequately removed during wet cleaning, atmospheric moisture absorption post-fab triggers galvanic corrosion [P1, P3]. Corrosion weakens the mechanical anchor between the bond pad and solder bump, leading to premature pad cratering during thermomechanical stress testing [P1, A2].

Passivation Micro-cracking and Moisture Ingress

The silicon nitride passivation cap possesses high intrinsic compressive stress [A2]. If the CB etch profile introduces sharp, angular geometries at the top opening rim, packaging encapsulation compounds exert localized shear forces at these high-stress points [A2]. Over thermal cycling, these stress concentrations initiate micro-cracks that propagate outward through the silicon nitride capping layer [P1, A2]. Once the protective nitride barrier is breached, atmospheric moisture and corrosive contaminants penetrate the BEOL stack, inducing inter-level metal oxidation and dielectric degradation across functional logic circuits [P1, A2].

Walk the Real Step

To see how this single process step connects with adjacent steps in the complete fabrication sequence, inspect the execution context within the primary module flow (Engineering Practice).

You can direct your focus to Open CB Step 262 in the interactive flow to observe the exact inputs, physical transformation, and verified structural output of this process step (Engineering Practice).

+-------------------------------------------------------------------+
|               Step 262: Contact Border (CB) Etch                  |
+-------------------------------------------------------------------+
|  Input State  : Patterned PR Mask over SiN/SiO2 Passivation Stack |
|  Action       : Fluorocarbon RIE Plasma Dual-Dielectric Erosion   |
|  Endpoint     : Optical Emission Signals Stop Etch at Top Metal   |
|  Output State : Precise Tapered Pad Opening with Pristine Metal   |
+-------------------------------------------------------------------+

During the physical execution of Step 262, the patterned wafer is clamped onto an electrostatic chuck within a temperature-controlled RIE chamber [P2, T1]. Backside helium cooling maintains wafer temperature stability to prevent thermal degradation of the photoresist mask during ion bombardment [T1]. Plasma ignition introduces the fluorocarbon gas mixture, initiating rapid directional erosion of the top silicon nitride cap followed by the silicon dioxide buffer [P2, T1]. Real-time optical emission spectroscopy continuously monitors specific radical wavelength emissions, detecting the sudden drop in carbon-oxygen byproduct intensity as the oxide is exhausted and halting main etch execution [T2]. A tailored over-etch phase clears residual dielectric pockets along pad corners, after which the wafer transfers directly to an integrated chamber for plasma ashing and subsequent chemical wet cleaning [P1, T1].

Related Learning Paths

Understanding the passivation opening etch mechanism requires evaluating its position between upstream BEOL interconnect fabrication and downstream packaging modules [P1, T2].

To expand your expertise across adjacent modules within the 28nm platform, review these detailed operational guides:

• Upstream Module Dependencies: Examine the structural foundation beneath the passivation stack through the 28nm Planar process flow [P4]. This comprehensive module guide details the dual-damascene copper interconnect architecture, low-k dielectric deposition, and top metal pad formation steps that establish the landing target for the CB etch [T1, T2].

• Downstream Assembly Integration: Trace the direct packaging transition following pad exposure in the 28nm Planar copper bump integration process flow [P4]. This module covers under-bump metallization sputtering, photoresist bump patterning, copper pillar electroplating, and solder reflow mechanics that directly depend on clean, structural pad openings [A1].

• Advanced Structural Extensions: Explore how opening techniques adapt to 3D heterogeneous integration using through-silicon via (TSV) architecture [A1] and how peripheral wafer-edge stress mitigation structures prevent film delamination during high-stress packaging processes [A2].

Future Outlook

As device scaling progresses beyond planar nodes into advanced three-dimensional architectures, the fundamental principles of oxide-nitride passivation etching continue to evolve to meet stringent integration demands [A1, A2].

+-------------------------------------------------------------------+
|               Emerging Passivation Etch Trends                    |
+-------------------------------------------------------------------+
|  1 [P4]. Atomic Layer Etching (ALE) for Zero Pad Sputtering & Recess   |
|  2 [P4]. Ultra-Fine Pitch Hybrid Bonding (Sub-Micron Pad Openings)     |
|  3 [A1]. Low-k / Low-Stress Alternative Passivation Dielectric Stacks  |
+-------------------------------------------------------------------+

Directional Atomic Layer Etching (ALE)

Conventional reactive ion etching faces severe challenges in meeting zero-recess requirements on delicate top metallization pads [P2, T1]. Advanced nodes are increasingly adopting directional atomic layer etching (ALE) techniques [T1]. By decoupling the etch process into self-limiting chemical adsorption phases and low-energy ion bombardment phases, directional ALE allows monolayer-by-monolayer removal of silicon nitride and oxide films [T1]. This achieves atomic-level control over sidewall profiles while eliminating ion-sputtering damage to underlying aluminum or copper landing pads [P4, T1].

Direct Hybrid Bonding Integration

The industry transition toward high-density chiplet integration and direct copper-to-copper hybrid bonding demands extreme planarization and sub-micron pad opening accuracy [A1]. Future passivation opening schemes must create planar, ultra-clean dielectric openings where metal pads and surrounding passivation surfaces align with zero topography step [A1]. Achieving this level of surface co-planarity requires combining high-selectivity dry etching with post-etch chemical mechanical planarization (CMP) to facilitate direct atomic diffusion bonding between stacked dies [A1, A2].

Low-Stress and Low-Temperature Passivation Dielectrics

To accommodate thermal budget constraints in multi-die heterogeneously integrated packages, novel low-temperature PECVD silicon nitride formulations and organic-inorganic hybrid passivations are replacing conventional high-temperature dielectrics [P1, A2]. These advanced films minimize intrinsic wafer warpage while reducing global thermal stress [A2]. Etch mechanisms must adapt to these modified film densities and chemical compositions, requiring modified fluorocarbon plasma chemistries to maintain high anisotropic selectivity, profile taper control, and defect-free pad opening integration [P2, A2].