Contact Barrier (CB) Dielectric Etch in 28nm: Physics, Integration Mechanisms, and Device Reliability

Function in the Complete Flow

In a 28nm Planar process flow, the contact barrier (CB) dielectric etch is the pivotal pattern-transfer step that opens vertical access vias through the composite contact dielectric stack. Positioned within the contact integration module, this operation selectively removes deposited oxide and nitride dielectric layers to expose underlying conductive landing areas—specifically silicide contacts over active source/drain regions and gate electrode structures.

By carving out precise vertical openings, the CB etch creates the physical pathways required to establish low-resistance electrical connections between transistor terminals and the lowest interconnect metal level. The fidelity and cleanliness of these contact openings directly determine parasitic series resistance, affecting transconductance and drive current in high-performance CMOS circuits.

+-------------------------------------------------------------+
|               Patterned Photoresist Mask                    |
+-------------------------------------------------------------+
|     Silicon Nitride (SiN) Capping / Hard Mask Layer         |
+-------------------------------------------------------------+
|     Silicon Dioxide (SiO2) Dielectric Stack                 |
+-------------------------------------------------------------+
|  Silicide Landing Pad / Gate Structure  | Active / STI      |
+-------------------------------------------------------------+

Executing this selective dielectric etch requires maintaining high directionality to preserve tight lateral pitch while achieving controlled termination at the underlying conductive interfaces. Under-etching leaves insulating dielectric remnants over the landing region, resulting in severe contact resistance degradation or electrical open circuits. Conversely, uncontrolled over-etching induces physical sputtering of silicide, micro-trenching into the underlying silicon substrate, or lattice damage that degrades junction leakage.

Upstream Input State

Prior to the CB etch operation, the front-end-of-line (FEOL) and middle-of-line (MOL) processing steps complete the active transistor structures, including gate patterning, spacer formation, source/drain junction engineering, and self-aligned silicide formation.

To insulate the gate and active structures before contact metallization, a composite dielectric barrier stack is blanket-deposited. This stack typically features a deposited silicon dioxide layer topped by a denser silicon nitride layer. The nitride layer acts as a barrier and hard mask, leveraging its higher chemical bond energy relative to oxide to enable controlled etch selectivity and structural stability.

Incoming Wafer Topography and Masking Architecture:

[ Lithography Photoresist Pattern ]
              |
              v
+-------------------------------------------------------------+
|  Silicon Nitride (SiN) Capping Layer                        |
+-------------------------------------------------------------+
|  Silicon Dioxide (SiO2) Dielectric Matrix                   |
+-------------------------------------------------------------+
|  Silicide Contact Pad (NiSi) / Gate Electrode               |
+-------------------------------------------------------------+

An anti-reflective layer and photoresist are applied and lithographically patterned to define the lateral position and critical dimension of the contact openings. The incoming wafer presents localized surface topography created by gate structures and active region steps. Consequently, the photoresist mask must accommodate variations in coating thickness while maintaining precise alignment over the narrow silicide landing targets.

Physical and Chemical Mechanisms

The CB dielectric etch is performed in a high-density plasma reactive ion etching chamber using fluorocarbon-based chemistries. The process relies on a synergy between chemical radical reactions and directional physical ion bombardment.

Etch Plasma Dynamics inside RIE Chamber:

   Fluorocarbon Plasma (CF4/C4F8 + Ar + O2)
                        |
                        v  [Plasma Dissociation]
        +-------------------------------+
        |  CFx+ Ions    |  F* Radicals  |
        +-------------------------------+
            |                 |
            v (Directional)   v (Chemical)
   Physical Sputtering    Surface Reaction & Polymerization
            \                 /
             v               v
   +------------------------------------+
   | Anisotropic Contact Etch Front     |
   +------------------------------------+

Dielectric Dissociation and Volatile Product Formation

Fluorine radicals generated in the plasma break Si-N and Si-O chemical bonds within the composite dielectric stack. Chemically, fluorocarbon plasma species react with the silicon dioxide and silicon nitride dielectric matrix to form volatile gaseous byproducts that are evacuated from the reactor chamber [T1]. In the oxide layer, oxygen liberated from the broken SiO2 network reacts with fluorocarbon radicals to produce carbon monoxide and carbon dioxide, helping maintain a steady-state polymer thickness at the etching surface.

Ion-Assisted Directionality and Profile Control

Physical ion bombardment accelerated across the plasma sheath provides vertical directionality, though increasing physical sputtering inherently reduces material selectivity [T1]. Energetic positive ions strike horizontal surfaces at normal incidence, sputtering away fluorocarbon polymer deposits and enhancing vertical etch rate relative to lateral erosion. On vertical feature sidewalls, where direct ion impact is minimal, fluorocarbon polymer fragments accumulate to form a protective passivating film. This balance between ion sputtering at the bottom and polymer accumulation along the perimeter establishes a controlled, slightly tapered contact profile, preventing undercut while ensuring seamless metal liner fill in subsequent steps.

Interface Detection and Controlled Termination

As the etch front approaches the underlying silicide or active region, the process transitions to an over-etch phase designed to clear residual dielectric corners across the wafer. Optical emission spectroscopy monitors characteristic plasma radical wavelengths. A sharp decrease in byproduct emission signals indicates that the dielectric layers have been cleared, triggering the transition to a lower-bias over-etch step to minimize silicide sputtering and substrate damage.

Post-Etch Ashing and Surface Clean

Following dry etching, the wafer is subjected to downstream oxygen- or hydrogen-based plasma ashing to combust remaining photoresist and cross-linked fluorocarbon polymers. A subsequent wet chemical clean removes trace inorganic residues and fluorine complexes from the exposed conductive surface without corroding the silicide interface.

Downstream Impact and Failure Propagation

The geometric profile, interface cleanliness, and structural integrity of the etched contact vias directly govern downstream metallization yield and long-term device reliability.

+-----------------------------------------------------------------+
|               CB Etch Process Marginality                       |
+-----------------------------------------------------------------+
               |                                   |
               v                                   v
   [ Incomplete Dielectric Etch ]        [ Excessive Over-Etch ]
               |                                   |
               v                                   v
   - High Contact Resistance             - Silicide Sputtering & Recess
   - Open-Circuit Failures               - Substrate Micro-Trenching
   - Poor Metal Plug Adhesion            - Elevated Junction Leakage
               |                                   |
               +-----------------+-----------------+
                                 |
                                 v
                 [ Transistor & Circuit Failure ]

Contact Resistance Spikes and Open Circuits

An ohmic contact is defined as a metal-semiconductor contact that has a negligible junction resistance relative to the total resistance of the semiconductor device [T2]. If the CB etch rate slows down due to excessive polymer deposition or premature endpoint detection, a thin interfacial dielectric residue remains at the bottom of the contact via. This residual insulating layer severely increases specific contact resistance or creates complete open-circuit failures, degrading drive current and switching speed.

Silicide Sputtering and Junction Leakage

If the over-etch step employs excessive ion bias energy or prolonged exposure, energetic ions breach the protective surface boundary and physically sputter the thin silicide layer. Sputtering reduces silicide thickness and creates micro-trenches at the contact perimeter. Sputtered metal atoms can also be re-deposited onto active junction boundaries, forming localized leakage paths that elevate off-state drain current.

Sidewall Profile Defect Dynamics

If sidewall polymer passivation is inadequate, lateral chemical erosion leads to profile undercut or bowing. Conversely, excessive polymer buildup produces an over-tapered contact with a constricted bottom critical dimension. Re-entrant or overly steep sidewalls compromise physical vapor deposition barrier and seed liner continuity, creating sub-micron voids during metal plug fill. These voids act as high-resistance bottlenecks and stress concentrators during electromigration testing. For further details on adjacent step mechanics, inspect the CB etch step in the contact module.