40nm BSI CMOS Image Sensor Metal-Six Interconnect Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

In a 40nm BSI CMOS Image Sensor process flow, the metal-six (MET6) interconnect module serves as one of the uppermost wiring tiers, bridging lower-level interconnects to bonding pads, peripheral logic, and readout circuitry [A2]. By the time the wafer reaches this module, the device has already passed through photodiode formation, front-end transistor fabrication, silicidation, and several lower metal levels [T1]. The MET6 module must deliver a continuous, low-resistance conductive path that can survive downstream passivation, backside thinning, and color filter array deposition without degrading pixel performance [P2].

The BSI architecture adds a unique constraint: because light enters from the backside after silicon thinning, the frontside metal stack must be fully formed and passivated before the wafer is flipped and thinned [P3]. This means the MET6 module is among the last frontside processing steps, and any defect or stress introduced here propagates through the entire backside thinning and packaging sequence [P4]. The metal-six layer also participates in electromagnetic shielding — in stacked sensor architectures, upper metal layers can serve as grounded shield structures that suppress parasitic coupling between pixel arrays and logic circuitry [A1][A2].

From a signal-integrity perspective, the MET6 interconnect carries analog readout signals, pixel reset lines, and power rails that must maintain low noise coupling to the underlying pixel array [A2]. The integration logic demands that this module not introduce topography that would compromise subsequent passivation lithography or pad opening [T1]. For a broader view of where MET6 sits in the overall 40nm BSI CMOS Image Sensor process flow, the complete module sequence and integration dependencies are essential context [P2].

Entry State and Sequence Logic

Upstream Dependencies

The MET6 module receives a wafer that has completed the sixth interlayer dielectric (ILD6) deposition and planarization [T1]. The ILD6 stack must provide sufficient planarity for MET6 lithography, because any residual topography from lower metal levels would transfer into the MET6 trench pattern and cause line-width variation or metal stringers [T1]. In the 40nm BSI CIS flow, the 40nm BSI CMOS Image Sensor sixth interlayer dielectric integration process flow directly precedes MET6, and the 40nm BSI CMOS Image Sensor via-five integration process flow establishes the vertical connections that MET6 must overlay and contact [A2].

The entry surface must be free of residues, particles, and native oxide patches that could block metal adhesion or create voids during deposition [P1]. Pre-metal cleaning steps, often involving a combination of physical and chemical removal mechanisms, ensure that the ILD6 surface is chemically active for the subsequent barrier and seed depositions [P1].

Downstream Deliverables

After MET6 patterning and metal fill, the wafer proceeds to final passivation — typically a silicon nitride or silicon oxynitride layer deposited by plasma-enhanced chemical vapor deposition (PECVD) — followed by pad opening and bonding pad formation [T1]. The MET6 surface topography, metal dishing, and dielectric erosion directly determine the quality of passivation coverage [P1]. If MET6 leaves excessive step height or metal protrusion, passivation may crack or delaminate during thermal cycling or packaging stress [P1].

In BSI flows, after frontside passivation, the wafer is bonded to a carrier substrate, flipped, and the silicon substrate is thinned to enable backside illumination [P3]. The mechanical stress of thinning and backside processing can propagate through the dielectric stack; the MET6 layer, being near the top of the frontside stack, must maintain structural integrity under these stresses [P1].

Physical and Chemical Mechanisms

METAL 6 TRENCH - Photo Integration Principles

The MET6 trench definition relies on photolithographic patterning using a krypton fluoride (KrF) lithography system (Engineering Practice). The fundamental principle is that the photoresist, upon exposure to the lithographic energy, undergoes a chemical transformation that alters its solubility in developer solution [P2]. The KrF lithography system is chosen for upper metal layers because the critical dimensions at this tier are sufficiently relaxed that deep ultraviolet exposure provides adequate resolution while maintaining high throughput (Engineering Practice).

The METAL 6 TRENCH - Photo integration principles center on the interaction between the resist profile, the underlying anti-reflective coating (ARC), and the ILD6 topography [A2]. The ARC layer absorbs reflected light from the substrate, preventing standing waves and notching in the resist profile [A2]. The quality of the resist sidewall angle and footing behavior directly determines the subsequent etch profile, which in turn governs metal gap-fill capability and final line resistance [T1].

For the 40nm BSI CIS node, the MET6 trench must accommodate the relatively wide metal lines used for power distribution and signal routing while maintaining clean trench sidewalls for barrier and metal deposition [P1]. The etch chemistry — typically a fluorocarbon-based plasma — selectively removes the ILD6 dielectric while preserving the photoresist mask and stopping cleanly on the etch-stop layer below [P1].

Metal Barrier and Seed Deposition

After trench formation, a diffusion barrier layer (commonly a refractory metal nitride) is deposited conformally along the trench sidewalls and bottom [A1]. The barrier serves two functions: it prevents metal atoms from diffusing into surrounding dielectrics or the underlying silicon device region, and it provides adhesion between the metal fill and the dielectric [A1][A2]. In CMOS image sensors, metal diffusion into the pixel region is particularly damaging because transition metal atoms create deep energy levels in the silicon bandgap, increasing dark current and white spot defects [P4].

The barrier deposition mechanism involves physical vapor deposition (PVD), where sputtered atoms arrive at the trench surface with sufficient energy to adhere and form a thin, conformal film [P3]. The seed layer, deposited immediately after or simultaneously with the barrier, provides a conductive nucleation surface for the subsequent electroplated metal fill [A2].

Electroplating and Chemical Mechanical Planarization

The bulk metal fill is deposited by electrochemical plating, where metal ions in solution are reduced at the wafer surface (cathode) and deposited into the trench [P4]. The plating chemistry must fill trenches without seams or voids — a challenge that depends on the trench aspect ratio, the seed layer continuity, and the plating additives that suppress deposition at the trench opening while accelerating it at the bottom (Engineering Practice).

Chemical mechanical planarization (CMP) then removes the overburden metal, leaving metal only within the trenches (Engineering Practice). The CMP mechanism combines mechanical abrasion from silica-based slurry particles with chemical dissolution of the metal surface [P1]. The selectivity between metal and dielectric removal rates determines the final metal dishing and dielectric erosion — parameters that directly affect downstream passivation quality and pad contact resistance [P1].

Silicide Contact Considerations

Although the MET6 module itself does not form silicide contacts, the interconnect chain it completes includes lower-level contacts to the pixel and peripheral transistor regions [P1]. The reliability of these TiSix contacts — formed in a silicide-last integration scheme — depends critically on the pre-clean sequence performed before barrier metal deposition [P1]. An Ar plasma combined with a Siconi™ remote plasma dry clean selectively removes native oxide from contact hole bottoms without damaging the underlying silicon lattice, enabling reliable low-resistance contacts [P1]. If any step in the MET6 module introduces contamination or particulates that reach these contact interfaces, the entire interconnect chain resistance can degrade [P1].

Interfaces and Failure Propagation

MET6-to-ILD6 Interface

The interface between the MET6 metal lines and the ILD6 dielectric is governed by adhesion chemistry and barrier integrity [T1]. Poor adhesion leads to delamination during thermal cycling, while barrier pinholes allow metal diffusion into the dielectric [P4]. In BSI CMOS image sensors, metal contamination that reaches the photodiode region creates generation-recombination centers, directly increasing dark current and degrading quantum efficiency [P4]. The proximity gettering approach — using hydrocarbon molecular ion implantation to create buried gettering sinks — can partially mitigate this risk by trapping diffused metals away from the device active region [P4]. However, gettering efficiency is finite, and the best strategy remains defect prevention at the MET6 interface [P4].

MET6-to-Passivation Interface

The MET6 surface condition after CMP — including metal dishing, dielectric erosion, and residual slurry — determines the quality of the passivation layer deposited on top [P1]. Excessive dishing creates a recessed metal surface that can trap moisture or contaminants, while metal protrusion creates stress concentration points in the passivation [P1]. Both conditions can lead to corrosion, electromigration, or dielectric breakdown over the device lifetime (Engineering Practice).

Noise Coupling to Pixel Array

In BSI CMOS image sensors, the frontside metal stack sits between the photodiode array and the backside illumination path [A1]. Although BSI architecture separates the metal stack from the optical path, electromagnetic coupling between MET6 signal lines and the underlying pixel transistors can introduce fixed-pattern noise and random telegraph signal (RTS) noise [P4]. Grounded shield structures in the interconnect stack — as described in stacked sensor patents — can suppress this coupling by providing a low-impedance reference plane between noisy interconnects and sensitive pixel nodes [A1][A2]. The MET6 layer, being the topmost metal, is well positioned to serve as a shielding plane if its layout and grounding are designed accordingly [A2].

Failure Mode: Metal Diffusion and Dark Current Degradation

A critical failure pathway in BSI CIS is metal atom diffusion from interconnect layers into the silicon device region [T1]. Transition metals such as Fe, Cu, and Ni introduce deep energy levels in the silicon bandgap that act as generation-recombination centers [P4]. These centers increase dark current, reduce carrier lifetime, and can create white spot defects visible in the final image [P2]. The barrier layer integrity at the MET6 level is therefore not merely an interconnect reliability concern — it is a pixel performance determinant [A2]. The pinned photodiode structure, which relies on surface potential pinning to suppress dark current [P3], is particularly sensitive to metal contamination because the p+ pinning layer can be compensated by donor-type metal impurities.

Failure Mode: Electromigration and Stress Migration

Upper metal levels in CMOS image sensors carry analog signals and power currents that, while lower than in high-performance logic, must flow continuously during image capture [A2]. Electromigration — the directional transport of metal atoms under electron wind force — can thin MET6 lines over time, eventually causing opens [P4]. The mechanism is governed by the balance between electron wind force and back-stress from the surrounding dielectric [T2]. Stress migration, driven by thermal expansion mismatch between metal and dielectric, can also create voids [P4]. Both failure modes are exacerbated by narrow line widths and high current densities, and their mitigation depends on barrier quality, grain structure control, and dielectric confinement stiffness [P2].

Walk the Real Module

To understand the MET6 module in its actual sequence context, engineers can explore the interactive process flow for the 40nm BSI CIS technology [T1]. The module's individual steps — from photoresist deposition and KrF exposure through trench etch, barrier deposition, metal fill, and CMP — are each represented with their integration dependencies and upstream/downstream connections [P2].

For the metal-six interconnect specifically, Open MET6 Step 232 in the interactive flow provides the step-level detail within the full 40nm BSI CMOS Image Sensor process flow [A2]. This interactive view allows engineers to trace how the MET6 module receives the planarized ILD6 surface and how its output — the patterned metal-six lines — feeds into the passivation and pad formation steps that follow [T1].

The step-level view also clarifies the MET6 module process flow logic: each step has a defined entry condition, a primary physical or chemical transformation, and a specified exit condition that the subsequent step depends on (Engineering Practice). Understanding these transitions is essential for diagnosing yield issues, because a failure observed at MET6 CMP may actually originate from a resist footing created during the METAL 6 TRENCH - Photo step, or from an ILD6 planarity issue inherited from the previous module (Engineering Practice).

Related Learning Paths

Engineers studying the MET6 module should also explore the adjacent modules that define its entry and exit conditions:

• The 40nm BSI CMOS Image Sensor process flow overview provides the complete module sequence and integration architecture, essential for understanding where MET6 fits in the overall device fabrication [T1].

• The sixth interlayer dielectric integration process flow is the immediate upstream module — the ILD6 planarity and etch-stop layer quality directly determine MET6 trench profile and metal fill quality [T1].

• The via-five integration process flow defines the vertical interconnect that MET6 must contact; the via resistance and alignment directly influence MET6 contact resistance and yield [T1].

Additionally, the interactive flow link above allows step-by-step navigation through the MET6 sequence, enabling engineers to trace cause-and-effect chains across module boundaries (Engineering Practice).

Future Outlook

Three-Dimensional Stacking and Interconnect Evolution

The trend toward three-dimensionally stacked CMOS image sensors — where the pixel array chip and logic chip are bonded face-to-face — is reshaping the role of upper metal layers like MET6 [A2]. In stacked architectures, an interposed layer between the pixel array and logic chip provides electrical connection, electromagnetic shielding, and metal diffusion barrier functions simultaneously [A1][A2]. This means future MET6-like layers may need to incorporate grounded shield regions and diffusion barrier materials as integral design elements, rather than treating these as afterthoughts to the interconnect layout [A2].

Reduced Thermal Budgets and Gettering Challenges

As CMOS image sensor fabrication adopts lower thermal budgets to accommodate 3D stacking and advanced dielectric materials, conventional intrinsic gettering based on oxygen precipitation becomes less effective [P4]. Proximity gettering using hydrocarbon molecular ion implantation offers a compatible alternative, but it requires careful integration with the interconnect process to ensure that gettering sinks remain stable through MET6 thermal cycles and that no new defect sources are introduced [P4]. The MET6 module, being late in the frontside flow, must be compatible with these gettering strategies — any elevated thermal step in the MET6 sequence could alter gettering sink morphology and reduce impurity capture efficiency [P4].

Pixel Shrink and Crosstalk Mitigation

As pixel pitches continue to shrink, the ratio of pixel pitch to optical absorption length decreases, exacerbating optical and carrier crosstalk between adjacent pixels [P3]. The frontside metal stack — including MET6 — can mitigate electrical crosstalk by providing grounded reference planes that isolate pixel signals [A2]. However, denser metal routing also increases parasitic capacitance, which can degrade conversion gain and increase readout noise [P2]. Future MET6 integration must balance the need for electromagnetic shielding against the parasitic load on sensitive pixel nodes, requiring co-optimization of metal layout, dielectric permittivity, and pixel circuit design [A2].

Advanced Cleaning and Contact Reliability

The continued scaling of contact dimensions in advanced CMOS image sensors demands ever-more-selective pre-clean processes [P1]. The Siconi™ remote plasma approach combined with Ar plasma demonstrates that hybrid physical-chemical cleaning can achieve the selectivity and damage control needed for reliable TiSix contacts [P1]. As MET6 integration increasingly involves contacts to scaled peripheral transistors, these advanced cleaning strategies will become integral to maintaining interconnect chain reliability across the full metal stack [P1].