40nm BSI CMOS Image Sensor ILD6 Integration: Process Flow Principles and Dielectric Physics

Role in the Complete Flow

In a 40nm back-side illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor fabrication sequence, the sixth interlayer dielectric (ILD6) module sits near the upper end of the multi-level metallization stack, bridging the gap between completed metal interconnect layers and the final passivation or bond-pad architecture. By the time the wafer arrives at this module, the front-side device region has already been fully formed: pinned photodiodes, transfer gates, floating diffusion nodes, and source-follower transistors are defined, while metal interconnects up to metal-six (MET6) have established signal routing from pixel and peripheral circuits. The ILD6 module receives a planarized surface following the Cu chemical-mechanical polishing (CMP) of the MET6 module, and it must deliver a sealed, low-defect dielectric barrier and capping layer stack suitable for subsequent bond pad opening or direct passivation, depending on the specific integration scheme.

Intermetal dielectrics are deposited dielectric layers designed to separate global metal interconnects from each other [T1]. The fundamental purpose of ILD6 is to electrically isolate the uppermost metal routing from the layers beneath while preserving the optical and electrical integrity that the pixel array demands. In a BSI image sensor, although light enters from the thinned backside, the front-side metallization still serves as a reflector that can boost quantum efficiency by redirecting photons back into the photodiode depletion region. This means the ILD6 stack must not only provide mechanical and dielectric isolation but also maintain optical flatness so that any reflective metal layer above or below it functions predictably. Furthermore, the ILD6 module must be thermally compatible with the constrained thermal budget of an advanced image sensor, where excessive thermal treatment can degrade dopant profiles in the pinned photodiode and increase dark current.

Within the broader 40nm BSI CMOS Image Sensor process flow, the ILD6 module acts as a crucial barrier: any contamination, moisture absorption, or stress mismatch introduced here propagates upward into subsequent bond-pad integration and connects back to metal-six interconnect integration. The dielectric must also act as a barrier against mobile ions and moisture that could drift toward the pixel active region under operating bias, a concern amplified by the fact that image sensor pixels are extremely sensitive to leakage and trap-assisted generation currents.

Entry State and Sequence Logic

Upstream Dependencies

When the wafer enters the ILD6 module, it arrives following the Cu CMP and post-CMP clean of the MET6 module, exposing the polished copper interconnects and Ta-based liner surface. The sequence logic demands that the preceding MET6 copper CMP has produced a smooth, defect-free surface without residual slurries, copper corrosion, or severe dishing and erosion. Because copper oxidizes rapidly when exposed to ambient air, the top surface of the MET6 copper interconnects is highly susceptible to native oxidation and outward metal diffusion prior to capping.

In a 40nm BSI CMOS image sensor specifically, the pixel-peripheral circuit boundary imposes additional sequence constraints. The pixel region requires strict control of defect states near the front surface. The ILD6 module must seal the exposed MET6 copper and Ta-based liner without inducing chemical damage or dielectric breakdown at underlying nodes, and any pre-deposition surface treatment must selectively reduce native oxides without damaging exposed dielectric or metal structures.

Downstream Deliverables

The ILD6 module must deliver: (1) a continuous, dense capping layer (ILD 6-1) that acts as a dielectric diffusion barrier and copper capping layer (CCL) to seal exposed Cu and Ta-based liners; (2) a thicker bulk dielectric (ILD 6-2) that balances diffusion blocking with overall capacitance reduction to address resistance-capacitance (RC) delay constraints; (3) a planarized top dielectric surface with controlled root-mean-square roughness to enable downstream bond pad cavity patterning; and (4) low residual film stress to prevent wafer warpage that would compromise backside thinning, color filter alignment, and microlens processing in later BSI-specific steps. The dielectric stack must also exhibit low outgassing, because trapped volatiles can migrate to interfaces and create white pixel defects or elevated dark current.

To achieve low parasitic capacitance while maintaining an effective hermetic seal, the dielectric module integrates a thin diffusion barrier capping layer followed by thicker bulk dielectric layers and subsequent caps prior to upper metallization or pad patterning.

Physical and Chemical Mechanisms

Copper Capping Layer (ILD 6-1) and Surface Pre-treatment Physics

The initial stage of the ILD6 stack, ILD 6-1, serves primarily as a dielectric diffusion barrier and copper capping layer. Following MET6 Cu CMP, native copper oxides (such as Cu2O or CuO) form almost immediately upon air exposure. If the capping dielectric is deposited directly onto oxidized copper, poor interfacial adhesion and elevated electromigration risk result. Therefore, prior to ILD 6-1 film growth, a controlled reductive pre-treatment (such as a reductive N2/H2 plasma) is applied to remove native Cu oxides without oxidizing the underlying metal or liner.

ILD 6-1 is typically deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD). Radiofrequency (RF) energy dissociates precursor gases into highly reactive plasma species, significantly lowering reaction activation energy and enabling film growth at relatively low temperatures to prevent thermal degradation of the underlying device structures. By tuning RF power and precursor chemistry, a dense amorphous silicon carbon nitride (a-SiNC:H) or oxygen-doped silicon carbide (a-SiCO:H) network is synthesized. Pure silicon nitride offers excellent diffusion blocking and high mechanical hardness, but its high dielectric constant exacerbates parasitic capacitance. Introducing carbon into the silicon nitride or carbide network lowers the dielectric constant, balancing thermodynamic barrier capability against parasitic capacitance penalty.

Bulk ILD Deposition and Dielectric Physics

Following ILD 6-1 deposition, the thicker bulk dielectric (ILD 6-2) is deposited to form the main body of the ILD6 module. Structurally separating a thin, dense capping layer (ILD 6-1) from a thicker bulk dielectric (ILD 6-2) is necessary to optimize electrical isolation while keeping overall dielectric constant low. ILD 6-2 can be deposited using PECVD or sub-atmospheric chemical vapor deposition (SACVD) with silane or tetraethyl orthosilicate (TEOS)-based chemistry.

During deposition, hydrogen content and stoichiometry must be carefully controlled. Excess hydrogen from plasma precursors can diffuse toward the underlying Si/SiO2 interface in the photodiode region, altering interface trap density and dark current. The polymerization reactions also generate water as a byproduct (forming Si-O-Si networks), which must be fully driven off by optimized deposition conditions or post-deposition thermal treatment so that the film remains dense, non-hygroscopic, and electrically stable.

Planarization and Stress Mechanics

After bulk dielectric deposition, surface planarization is carried out by chemical-mechanical polishing (CMP) when necessary to prepare for subsequent lithography. Chemical mechanical planarization has enabled IC manufacturing in achieving economically-viable global and local planarity across the entire wafer surface [P2]. The mechanics of CMP involve mechanical abrasion by silica slurry particles combined with chemical etching by the slurry's pH-active chemistry. Conceptually, the removal rate follows Preston's equation: removal is proportional to applied pressure and relative velocity between the wafer and polishing pad.

Residual stress in the ILD6 stack is a critical structural concern. PECVD SiO2 and SiCN/SiNC films exhibit tensile or compressive stress depending on deposition parameters, plasma power, and temperature. Stress mismatch between ILD6 sub-layers, capping dielectrics, and underlying metal lines can cause wafer bowing. In a BSI image sensor, wafer bow is particularly problematic because the wafer will later be bonded to a handle wafer, thinned from the backside, and subjected to color filter and microlens alignment — any curvature introduced at ILD6 propagates through these steps and degrades overlay accuracy.

Interfaces and Failure Propagation

ILD 6-1 to MET6 Copper/Liner Interface

The interface between ILD 6-1 and the underlying MET6 copper and Ta-based liner is a critical failure propagation path. If native oxide reduction prior to ILD 6-1 deposition is incomplete, or if precursor gases react aggressively with exposed Cu, weak interfacial bonding occurs. Under thermal cycling or electrical bias, weak adhesion at this interface leads to delamination or interface voiding, accelerating copper electromigration. In image sensors, mechanical delamination can cause local light blockage or particle creation, resulting in pixel defect clusters.

Interface Traps and Photodiode Surface Potential

Within the multi-layer ILD6 stack, dielectric-to-dielectric interfaces (such as SiNC-to-SiO2) are chemically distinct. Nitrogen- and carbon-containing amorphous networks meet network-forming oxide glass. Poor interface quality can create charge trap states that fill or empty under operating electric fields. Trapped charges in upper dielectric levels induce fringing fields or threshold voltage shifts in nearby peripheral transistors and perturb the electrostatic potential of the pinned photodiode. In a 40nm BSI sensor, maintaining stable surface potential in the pinned photodiode is essential to prevent unwanted carrier generation and image lag.

Moisture Ingress and Ionic Drift Pathways

Bulk oxides deposited by high-rate CVD techniques can be slightly porous or hygroscopic. Absorbed moisture introduces mobile ionic species (e.g., Na+, K+) that drift under electric fields. If moisture penetrates through pinholes or micro-cracks in the capping layers, mobile ions migrate toward the Si/SiO2 interface in the photodiode array. Accumulated ionic charge alters surface potential, degrades quantum efficiency, and creates generation centers that elevate dark current over device operating lifetime.

Thermal Budget and Dark Current Trade-offs

The deposition and densification of ILD6 films require thermal energy. However, in a 40nm BSI CMOS image sensor, the thermal budget is strictly limited. High temperatures cause dopant diffusion in the shallow p+ surface layer of the pinned photodiode, flattening the potential profile and weakening the drift field required for efficient charge collection. Consequently, ILD6 deposition is optimized toward plasma-enhanced lower-temperature processes, balancing dielectric density against pixel thermal limits.

Stress-Induced Dark Current Generation

Residual mechanical stress from the ILD6 stack transfers through the metal-dielectric lattice to the underlying silicon substrate. Mechanical strain alters the silicon band structure via deformation potential effects, shifting band edges and increasing thermal carrier generation rates at interface traps. High localized stress can even induce dislocations in silicon, acting as permanent generation centers that cause severe white pixel defects.

Walk the Real Module

To see how these principles translate into an actual process sequence, readers can Open ILD6 Step 242 in the interactive flow. This step represents the ILD 6-1 deposition entry point within the verified 40nm BSI CMOS image sensor process flow. By examining the step in context, engineers can observe how the capping layer deposition follows MET6 copper CMP and seals the exposed Cu/liner before bulk dielectric growth and bond pad patterning.

The interactive flow also illustrates how the ILD6 module connects to adjacent modules: upstream, MET6 interconnect integration defines the starting topography and exposed surface state; downstream, bond pad integration builds upon the hermetic capping and dielectric planarization provided by ILD6.

Related Learning Paths

For engineers seeking to deepen their understanding of the 40nm BSI CMOS image sensor architecture, several adjacent topics provide complementary context:

• The 40nm BSI CMOS Image Sensor process flow overview provides the full-module context into which ILD6 fits.
• The metal-six interconnect integration article details the immediate upstream process module.
• The bond-pad integration process flow article explains how the final passivation and pad cavity stack build upon ILD6.

Additionally, the physics of the pinned photodiode, which ILD6 must protect from thermal and mechanical disturbance, requires careful control of front-side stress, while gettering and defect passivation strategies complement the dielectric stack in suppressing dark current.

Future Outlook

Looking forward, the ILD6 module in advanced BSI image sensors faces several emerging integration requirements. As pixel sizes continue to shrink and metal stack heights increase to accommodate three-dimensional stacking and high-speed peripheral interconnects, effective diffusion barrier performance and stress management become increasingly critical.

In three-dimensionally stacked CMOS image sensors (3D-CIS), where pixel tiers and logic tiers are joined via direct hybrid bonding, upper dielectric layers play an active role in surface planarity and thermal budget allocation. The constrained thermal budget of bonded wafers drives ILD capping and bulk dielectric deposition toward low-temperature PECVD and atomic layer deposition (ALD) techniques. Furthermore, tuning carbon and nitrogen concentrations in amorphous silicon alloy caps continues to advance, enabling lower dielectric constants without sacrificing moisture barrier or electromigration suppression performance.