40nm BSI CMOS Image Sensor ILD6 Integration: Process Flow Principles and Dielectric Physics

Role in the Complete Flow

In a 40nm back-side illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor fabrication sequence, the sixth interlayer dielectric (ILD6) module sits near the upper end of the multi-level metallization stack, bridging the gap between the completed metal interconnect layers and the final passivation or bond-pad architecture [T1]. By the time the wafer arrives at this module, the front-side device region has already been fully formed: pinned photodiodes, transfer gates, floating diffusion nodes, and source-follower transistors are defined, while lower metal levels (metal-one through metal-five) have established signal routing from pixel and peripheral circuits [P3]. The ILD6 module receives a topography shaped by the preceding metal-five layer and its associated dielectric capping, and it must deliver a planarized, low-defect dielectric surface suitable for subsequent metal-six deposition or direct passivation, depending on the specific integration scheme [P4].

The fundamental purpose of ILD6 is to electrically isolate the uppermost metal routing from the layers beneath while preserving the optical and electrical integrity that the pixel array demands [T1]. In a BSI image sensor, although light enters from the thinned backside, the front-side metallization still serves as a reflector that can boost quantum efficiency by redirecting photons back into the photodiode depletion region [P3]. This means the ILD6 stack must not only provide mechanical and dielectric isolation but also maintain optical flatness so that any reflective metal layer above or below it functions predictably [T1]. Furthermore, the ILD6 module must be thermally compatible with the constrained thermal budget of an advanced image sensor, where excessive thermal treatment can degrade dopant profiles in the pinned photodiode and increase dark current [P1].

Within the broader 40nm BSI CMOS Image Sensor process flow, the ILD6 module is a gatekeeper: any contamination, moisture absorption, or stress mismatch introduced here propagates upward into the metal-six interconnect integration and ultimately into the bond-pad integration [P4]. The dielectric must also act as a barrier against mobile ions and moisture that could drift toward the pixel active region under operating bias, a concern amplified by the fact that image sensor pixels are extremely sensitive to leakage and trap-assisted generation currents [P4].

Entry State and Sequence Logic

Upstream Dependencies

When the wafer enters the ILD6 module, the surface consists of patterned metal-five lines embedded in the fifth interlayer dielectric, typically capped by an etch-stop or barrier layer such as silicon carbonitride (SiCN) [T1]. The sequence logic demands that the preceding metal etch and dielectric fill have already achieved a target sidewall profile and gap-fill density; if voids or seams exist in the underlying dielectric, the ILD6 deposition will inherit and amplify them [T1]. The entry surface roughness and metal step height directly determine how much planarization the ILD6 module must accomplish, and the SiCN cap layer serves as both a chemical-mechanical polishing (CMP) stop and a diffusion barrier that prevents copper or aluminum migration into ILD6 [T1].

In a 40nm BSI CMOS image sensor specifically, the pixel-peripheral circuit boundary imposes additional sequence constraints [P1]. The pixel region may employ silicide-last integration, where titanium silicide contacts are formed late in the flow to minimize metal proximity to photodiodes [P2]. This means ILD6 deposition must not disturb the fragile silicide interface at contact bottoms, and any pre-deposition surface treatment must be selective enough to avoid etching exposed silicon or silicide [P2].

Downstream Deliverables

The ILD6 module must deliver: (1) a continuous, void-free dielectric film with sufficient density to block moisture and mobile ions; (2) a planarized top surface with controlled root-mean-square roughness to enable metal-six lithography; (3) a stable interface with any SiCN or silicon nitride cap so that subsequent etch steps do not delaminate; and (4) low stress to prevent wafer warpage that would compromise backside thinning and color filter alignment in later BSI-specific steps [P3]. The dielectric must also exhibit low outgassing, because trapped volatiles can migrate to interfaces and create white pixel defects or elevated dark current, which are critical failure modes in image sensors [P4].

Physical and Chemical Mechanisms

ILD6 Deposition Chemistry

The sixth interlayer dielectric in a 40nm BSI image sensor is typically deposited using plasma-enhanced chemical vapor deposition (PECVD) or sub-atmospheric chemical vapor deposition (SACVD), relying on silane-based or tetraethyl orthosilicate (TEOS)-based precursor chemistry [T1]. In a TEOS-ozone SACVD reaction, the precursor undergoes decomposition and oxidation to form silicon dioxide (SiO₂), but the resulting film can be porous and hygroscopic, absorbing moisture that degrades dielectric reliability and can drift under bias [P2]. To mitigate this, the deposition is often structured as a multi-layer sandwich: a thin, dense PECVD underlayer acts as a moisture barrier, followed by a thicker SACVD bulk fill for conformal gap-fill, and a thin PECVD or SiCN overlayer that seals the stack [T1].

The ILD 6-1 deposition integration principles center on balancing conformality, film density, and hydrogen content [P4]. Conformality is needed to fill narrow gaps between metal lines without creating keyhole voids; density is needed to prevent moisture ingress; and hydrogen content must be controlled because excess hydrogen can passivate or depassivate dangling bonds at the Si/SiO₂ interface in the pixel region, altering dark current [P4]. The deposition reaction also produces water as a byproduct of polymerization (Si-O-Si bond formation), and this water must be driven off by a thermal treatment before the film is considered stable [T1].

SiCN Barrier and Etch-Stop Physics

Silicon carbonitride (SiCN) is frequently used as a cap or etch-stop layer within the ILD6 stack [P2]. The incorporation of carbon into silicon nitride modifies the band structure and reduces the dielectric constant relative to pure silicon nitride, which helps reduce parasitic capacitance between metal-six and metal-five lines [P2]. SiCN also exhibits higher hardness and lower stress than silicon nitride, making it a better mechanical buffer during CMP [P2]. From a chemical standpoint, SiCN is resistant to fluorine-based etch chemistries used in metal-six patterning, providing selectivity that prevents over-etch into ILD6 [T1].

The integration logic for placing SiCN between ILD6 sub-layers is to create a hard mask and barrier dual-function layer [P2]. During metal-six lithography and etch, the SiCN layer stops the etch cleanly; during subsequent dielectric deposition, it blocks copper diffusion [P2]. The carbon content in SiCN must be tuned: too much carbon degrades adhesion to adjacent oxide, risking delamination; too little carbon raises the dielectric constant and increases capacitance penalty [P2].

Planarization and Stress Mechanics

After ILD6 deposition, the surface is planarized by CMP [T1]. The physics of CMP involves mechanical abrasion by silica slurry particles combined with chemical etching by the slurry's pH-active chemistry [P2]. The removal rate depends on the Padney-Montanari Preston equation conceptually: removal is proportional to applied pressure and relative velocity (Engineering Practice). In the ILD6 module, CMP must remove the overburden of deposited oxide down to the SiCN stop layer or to a target remaining thickness, while minimizing dishing over wide metal pads and erosion in dense metal regions [P2].

Residual stress in the ILD6 stack is a critical concern (Engineering Practice). PECVD SiO₂ films tend to exhibit tensile or compressive stress depending on deposition conditions, and mismatched stress between ILD6, SiCN, and the underlying metal can cause wafer bowing [T1]. In a BSI image sensor, wafer bow is particularly problematic because the wafer will later be bonded to a handle wafer, thinned from the backside, and subjected to color filter and microlens alignment — any curvature introduced at ILD6 propagates through these steps and degrades overlay accuracy [P3].

Interfaces and Failure Propagation

ILD6-to-Metal-5 Interface

The interface between the deposited ILD6 and the underlying metal-five CMP surface is a primary failure propagation path [P4]. If the metal-five surface has residual copper oxide or corrosion from prior processing, the ILD6 deposition will nucleate on a contaminated surface, creating weak adhesion zones that can delaminate during thermal cycling (Engineering Practice). In image sensor pixels, such delamination is catastrophic because it can block light paths or create particulate contamination that manifests as black or white pixel defects [P1].

ILD6-to-SiCN-to-ILD6 Sub-layer Interface

Within the multi-layer ILD6 stack, the SiCN-to-oxide interface is chemically distinct [P2]. SiCN is a nitrogen-rich, carbon-containing ceramic, while the adjacent oxide is a network-forming glass (Engineering Practice). The bonding at this interface relies on Si-N and Si-O bridges, and poor interface quality can create trap states that charge under operating bias, shifting threshold voltages of nearby transistors or creating fixed charge that perturbs the pinned photodiode potential [P3]. In a 40nm BSI CMOS image sensor, where the pinned photodiode surface potential must be tightly controlled to suppress dark current and image lag, any charge injection from ILD6 interfaces is a direct threat to pixel performance [P1].

Moisture and Ion Diffusion Pathways

SACVD TEOS-ozone films are inherently porous and can absorb moisture from the ambient or from subsequent wet processing steps [T1]. Absorbed water introduces mobile ionic species, particularly sodium and potassium, that can drift under electric field and accumulate at the Si/SiO₂ interface of the photodiode, creating fixed charge that degrades UV sensitivity and increases dark current [P1]. The PECVD underlayer and SiCN cap function as diffusion barriers, but if any pinhole or crack exists, moisture will find a pathway [P4]. The failure mode is gradual: dark current increases over device lifetime, and white pixel defects emerge in elevated-temperature operating life testing [P4].

Thermal Budget Trade-offs

The ILD6 deposition and post-deposition cure involve thermal treatment to densify the film and drive off moisture [T1]. However, in a 40nm BSI image sensor, the thermal budget is constrained because high temperatures cause dopant diffusion in the pinned photodiode, flattening the p+ surface pinning layer and degrading the drift field that collects UV-generated carriers [P1]. The integration challenge is that ILD6 needs enough thermal energy to densify, but the pixel cannot tolerate it [P1]. This directional tradeoff pushes the ILD6 module toward lower-temperature deposition techniques and longer, lower-temperature cure cycles, accepting some residual porosity in exchange for pixel fidelity [P1].

Stress-Induced Dark Current

Residual compressive or tensile stress in the ILD6 stack can mechanically strain the underlying silicon lattice in the pixel region [T1]. Stress modifies the band structure through deformation potential interaction, shifting band edges and altering the generation-recombination rate at the Si/SiO₂ interface [T2]. In extreme cases, stress can create micro-cracks or dislocations that act as generation centers, directly increasing dark current (Engineering Practice). The ILD6 module must therefore balance film density (which favors higher deposition energy and stress) against mechanical gentleness on the pixel (Engineering Practice).

Walk the Real Module

To see how these principles translate into an actual process sequence, readers can Open ILD6 Step 242 in the interactive flow (Engineering Practice). This step represents the ILD6 module entry within the verified 40nm BSI CMOS image sensor process flow [P1]. By examining the step in context, engineers can observe how the ILD6 deposition is sequenced relative to metal-five CMP, SiCN cap deposition, and the subsequent metal-six patterning, confirming the integration dependencies discussed above [P4].

The interactive flow also illustrates how the ILD6 module connects to adjacent modules: upstream, the metal-five integration defines the entry topography; downstream, the metal-six interconnect and bond-pad modules depend on the planarity and integrity that ILD6 delivers [T1]. Understanding this contextual placement is essential for troubleshooting cross-module issues such as CMP erosion, metal line corrosion, or overlay drift [P4].

Related Learning Paths

For engineers seeking to deepen their understanding of the 40nm BSI CMOS image sensor architecture, several adjacent topics provide complementary context:

• The 40nm BSI CMOS Image Sensor process flow overview provides the full-module context into which ILD6 fits [P1].
• The metal-six interconnect integration article details the immediate downstream consumer of the ILD6 planarized surface [T1].
• The bond-pad integration process flow article explains how the final passivation stack builds upon the uppermost ILD layers [P4].

Additionally, the physics of the pinned photodiode, which ILD6 must protect from thermal and mechanical disturbance, is reviewed comprehensively in [P3], while gettering and defect passivation strategies that complement ILD6's role in suppressing dark current are discussed in [P4].

Future Outlook

Looking forward, the ILD6 module in advanced BSI image sensors faces several emerging pressures (Engineering Practice). As pixel sizes continue to shrink and metal stack heights increase to accommodate three-dimensional stacking and pixel-peripheral interconnects, the gap-fill and planarization challenges for ILD6 intensify [A1]. Researchers are exploring flowable chemical vapor deposition (FCVD) and spin-on dielectric technologies that can fill narrower, higher-aspect-ratio gaps than conventional SACVD, though these introduce their own porosity and outgassing concerns [T1].

Another trend is the migration toward three-dimensionally stacked CMOS image sensors (3D-CIS), where the pixel tier and logic tier are bonded via copper-to-copper hybrid bonding [P4]. In such architectures, the ILD6 module may serve as part of the bonding interface or may be replaced by a thinner, specialized bonding dielectric [T1]. The thermal budget constraints become even tighter in 3D-CIS because the bonded logic tier cannot tolerate high temperatures, pushing ILD6 deposition toward plasma-enhanced or spatial ALD techniques that achieve dense films at lower thermal cost [P4].

Finally, the role of SiCN and related silicon carbonitride alloys is evolving (Engineering Practice). Researchers are investigating carbon-rich, nitrogen-lean variants that further reduce dielectric constant while maintaining barrier performance, as well as ALD-deposited SiCN that offers conformal coverage in high-aspect-ratio structures [P4]. These innovations aim to reduce parasitic capacitance in the upper metal levels, improving signal speed in the peripheral readout circuitry without compromising the pixel dark current performance that remains the defining metric of a high-quality BSI CMOS image sensor [P1][P4].