40nm BSI CMOS Image Sensor Metal-Five Interconnect Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

In a 40nm backside illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor, the metal-five (MET5) interconnect module occupies a critical position near the top of the frontside interconnect stack [A2]. The module receives a wafer that has already completed lower metal levels—typically metal-one through metal-four—along with their associated via connections and interlayer dielectric (ILD) layers [T1]. At entry, the surface consists of a planarized dielectric stack with exposed underlying metal-four landing pads, ready to receive the fifth-level metallization that will serve as the uppermost routing layer before passivation and backside processing [T1].

The MET5 module must deliver a continuous, low-resistance interconnect layer that routes pixel readout signals, bias lines, and peripheral logic connections to bonding pads or through-silicon via (TSV) landing regions [A2]. In a BSI architecture, frontside metallization also functions as an optical reflector that redirects photons back toward the photodiode, effectively boosting quantum efficiency [P2]. This dual electrical–optical role distinguishes the MET5 module from a generic logic interconnect: the metal pattern density and reflectivity directly influence the optical path, while the electrical integrity governs readout fidelity [A2].

Downstream, the MET5 layer interfaces with final passivation deposition, pad opening, and—critically for BSI—the wafer bonding and thinning sequence that transfers the active silicon to a carrier substrate [T1]. Any topography, contamination, or metal protrusion left by the MET5 module propagates into the bonding interface, potentially causing bonding voids or backside thinning non-uniformity (Engineering Practice). For a broader view of where MET5 sits within the complete 40nm BSI CMOS Image Sensor process flow, the interconnect stack is one of several sequentially dependent modules that together define sensor performance [A2].

Entry State and Sequence Logic

Integration Dependencies Before MET5

The MET5 module cannot begin until the fifth interlayer dielectric (ILD5) has been deposited and planarized over the metal-four layer (Engineering Practice). This dielectric provides both electrical isolation and the mechanical surface upon which MET5 trenches will be patterned (Engineering Practice). The 40nm BSI CMOS Image Sensor fifth interlayer dielectric integration process flow establishes the chemical-mechanical planarization (CMP) surface quality and residual topography that directly determine MET5 lithographic fidelity [P1].

Additionally, the via-four module must be complete, providing vertical electrical connections from metal-four to the MET5 landing pads (Engineering Practice). The 40nm BSI CMOS Image Sensor via-four integration process flow ensures that via recesses or protrusions are controlled, because any via-top irregularity translates into MET5 trench bottom discontinuities that can cause metal thinning or opens [T1].

Sequence Logic After MET5

Once MET5 is patterned and the metal is deposited and planarized, the wafer proceeds to passivation layer deposition—typically a silicon nitride or silicon oxynitride film deposited by plasma-enhanced chemical vapor deposition (PECVD) [T1]. This passivation seals the MET5 surface against moisture and ionic contamination, then pad openings are etched to expose bonding pads [P1]. For BSI sensors, the frontside is then temporarily bonded to a carrier wafer, the original substrate is thinned or removed to expose the photodiode backside, and permanent color filter and microlens arrays are formed [P2]. The MET5 surface flatness is therefore a prerequisite for robust temporary bonding (Engineering Practice).

Physical and Chemical Mechanisms

METAL 5 TRENCH – Photo Integration Principles

The MET5 module process flow begins with photolithographic patterning of the metal-five trench (Engineering Practice). At the 40nm node, krypton fluoride (KrF) lithography is commonly employed for image sensor interconnect layers because the critical dimensions of pixel routing lines and peripheral logic interconnects fall within the practical resolution envelope of this exposure technology [A2]. The METAL 5 TRENCH – Photo integration principles center on transferring a reticle pattern into a photoresist layer that has been coated over the ILD5 surface [A2].

The core physical mechanism is the photochemical reaction within the resist: incident photons break photoactive compound bonds, altering solubility in the developer solution [T1]. The depth of focus budget is constrained by the residual topography inherited from underlying layers, making ILD5 planarization quality a controlling factor [T1]. In BSI image sensors, the MET5 trench pattern often includes large-area reflective metal plates interleaved with narrow routing lines, creating a large pitch-range layout that challenges both exposure dose uniformity and etch loading uniformity [A2].

Trench Etch Chemistry

After resist patterning, the trench is etched into the ILD5 dielectric using a fluorocarbon-based plasma (Engineering Practice). The etch mechanism involves simultaneous radical-driven chemical etching of the dielectric and ion-bombardment-enhanced removal of reaction byproducts [P1]. The etch selectivity to the underlying metal-four landing pad is critical: insufficient selectivity erodes the landing pad surface, increasing contact resistance, while excessive polymer deposition on trench sidewalls can create metal voids during subsequent metal fill [T1].

The directional nature of the etch—anisotropy produced by vertically accelerated ions—ensures that trench sidewalls are nearly vertical, which is essential for achieving the narrow metal lines required at this node (Engineering Practice). Sidewall polymer passivation during etch prevents lateral undercut, preserving the trench critical dimension that directly controls the final metal line width [P4].

Metal Deposition and Planarization

Following trench formation, a barrier/liner layer—typically based on tantalum or titanium compounds—is deposited by physical vapor deposition (PVD) or atomic layer deposition (ALD) to prevent metal diffusion into surrounding dielectrics [T1]. This barrier function is especially important in image sensors, where metal contamination in the photodiode region can introduce dark current and white pixel defects [A1]. A seed layer is then deposited, followed by electroplated copper or an alternative metallization that fills the trenches (Engineering Practice).

CMP removes the overburden metal and barrier material, leaving metal only within the trenches (Engineering Practice). The CMP mechanism combines mechanical abrasion by colloidal particles with chemical dissolution of the metal surface (Engineering Practice). The dishing effect—where wide metal features recess below the dielectric surface—is a key concern because MET5 often contains both narrow routing lines and wide reflective plates, creating a pattern-density range that challenges CMP uniformity [T1].

Interfaces and Failure Propagation

Upward Interface: Passivation and Bonding

The top surface of the MET5 layer becomes the interface for passivation deposition and, subsequently, temporary wafer bonding in the BSI process [T1]. Metal dishing or dielectric erosion from CMP creates localized height variations that can trap air or residue at the bonding interface, leading to bonding voids that compromise mechanical stability during backside thinning [P2]. If the passivation layer cannot conformally seal a dished metal region, moisture ingress paths form that accelerate metal corrosion and electromigration failures during reliability stress [P1].

Downward Interface: Via-Four and Metal-Four

At the bottom of the MET5 trench, the metal must establish reliable contact with the underlying via-four/metal-four structure (Engineering Practice). If the trench etch over-etches into the via material, the via top recesses and creates a narrow neck at the MET5 interface, increasing current density and electromigration risk [P4]. Conversely, if etch fails to fully clear dielectric residue from the via top, a high-resistance contact forms that degrades signal integrity—particularly problematic for the low-noise readout paths in CMOS image sensors [P4].

Optical Interface Considerations

In BSI sensors, the MET5 pattern serves as a frontside reflector [A2]. The metal fill ratio and surface smoothness after CMP determine the fraction of backside-incident photons reflected back toward the photodiode [P1]. A rough or heavily dished metal surface scatters light rather than reflecting it specularly, reducing the effective quantum efficiency improvement that the reflector is designed to provide [P2]. Moreover, metal lines that are too wide relative to the pixel pitch can create optical shadowing or diffraction artifacts that degrade the modulation transfer function [P4].

Failure Mode Summary

The dominant failure modes propagated from the MET5 module include: (1) metal opens from trench sidewall polymer residue blocking metal fill; (2) high-resistance via contacts from etch residue or over-etch; (3) bonding voids from CMP dishing; (4) dark current degradation from metal contamination if the barrier layer is compromised [A1]; and (5) reflectivity loss from surface roughness. Each failure mode traces back to a specific process step—lithography, etch, barrier deposition, or CMP—and the tradeoffs between steps are inherently directional (Engineering Practice). For instance, aggressive trench etch improves via clearing but worsens landing pad erosion; aggressive CMP improves planarity but increases metal dishing in wide features (Engineering Practice).

Walk the Real Module

To explore the actual step-by-step execution of the MET5 module within the 40nm BSI CMOS Image Sensor process flow, readers can Open MET5 Step 216 in the interactive flow [P4]. This interactive resource allows you to trace how each process step—resist coating, KrF exposure, development, trench etch, barrier deposition, metal fill, and CMP—sequentially transforms the wafer state and how upstream topology from ILD5 and via-four influences the final MET5 profile [T1].

Understanding the 40nm metal-five interconnect integration in the context of the full 40nm BSI CMOS Image Sensor process flow reinforces how each module's output becomes the next module's input constraint, and how the MET5 module uniquely carries both electrical and optical responsibilities that generic logic interconnect flows do not [P1].

Related Learning Paths

Engineers studying the MET5 module benefit from exploring adjacent process modules that share integration interfaces:

• ILD5 Module: The dielectric layer directly beneath MET5 governs surface planarity and trench etch depth control [P1]. Studying the ILD5 deposition and CMP steps illuminates why topography management upstream is the most powerful lever for MET5 yield improvement [P1].
• Via-Four Module: The vertical connection between metal-four and MET5 depends on via-four recess control and barrier continuity (Engineering Practice). This module's etch and fill quality directly sets the MET5 contact resistance distribution (Engineering Practice).
• Pixel and Photodiode Physics: Understanding pinned photodiode operation [P2] and floating diffusion capacitance engineering [P4] helps engineers appreciate why metal interconnect parasitics—particularly capacitance from MET5 routing over sensitive nodes—must be minimized to preserve conversion gain and reduce readout noise.
• Stacked Sensor Integration: For sensors employing three-dimensional stacking with interposer layers between pixel and logic chips [A1], the MET5 layer may also serve as a landing pad for TSV connections, adding another interface constraint to its design.

Future Outlook

The evolution of 40nm BSI CMOS image sensors is driving several trends that will reshape MET5 integration [P3]. First, as pixel sizes continue to shrink, the MET5 routing density increases while the reflective plate area decreases, intensifying the tension between electrical routing requirements and optical reflectivity [P4]. Advanced patterning techniques—such as double exposure or directed self-assembly—may be needed to extend KrF lithography capability without migrating to more expensive immersion tools [P1].

Second, the adoption of three-dimensional stacked image sensors, where pixel and logic wafers are bonded face-to-face, changes the MET5 role [A1]. When signal routing moves to the logic wafer through TSVs, the pixel-side MET5 can be simplified toward primarily optical functions—reflective plates and light shields—reducing routing complexity but increasing the importance of surface flatness for bonding yield [A1].

Third, the drive toward photon-countable sensitivity demands ever-lower parasitic capacitance at the floating diffusion node [P4]. MET5 routing that crosses over or near these nodes contributes parasitic coupling capacitance that directly degrades conversion gain [P4]. Future MET5 designs may employ thicker ILD5 or air-gap dielectric structures to reduce this coupling, requiring co-optimization of the ILD5 and MET5 modules [P4].

Finally, alternative barrier and liner materials—moving from PVD tantalum-based barriers toward ALD alternatives—offer better conformality in narrow trenches but introduce new integration challenges in CMP selectivity and adhesion (Engineering Practice). The interaction between barrier material choice, trench profile, and CMP dishing behavior represents an ongoing optimization frontier for 40nm BSI CMOS image sensor metal-five interconnect integration [A2].