40nm BSI CMOS Image Sensor Dual Gate-Oxide Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The 40nm BSI CMOS Image Sensor dual gate-oxide (DGOX) integration module occupies a pivotal position within the overall front-end-of-line (FEOL) process sequence. It serves as the bridge between active-region definition—where shallow trench isolation (STI) and well implants establish the pixel and peripheral device substrates—and the gate stack formation that follows. The module's primary function is to establish two distinct gate-oxide thicknesses on the same silicon wafer: a thicker thermal oxide optimized for higher-voltage pixel transfer (TX), reset (RST), and select (SEL) transistors, and a thinner thermal oxide tailored for high-speed, lower-voltage peripheral logic transistors.

In a 40nm backside-illuminated (BSI) sensor, pixel operations require complete charge transfer from the pinned photodiode (PPD) to the floating diffusion (FD) node. Achieving this complete charge transfer without dielectric breakdown or excessive gate leakage demands an operating voltage higher than the standard core logic supply. Conversely, peripheral readout circuits demand thinner gate dielectrics to maximize transconductance, switching speed, and power efficiency. The DGOX module ensures these two distinct device families can coexist on a single die without compromising the reliability or electrostatics of either domain.

Incoming wafers arrive from isolation and well implantation carrying a thin sacrificial or screen oxide that protected active silicon during ion implantation. The DGOX module replaces this damaged dielectric with pristine, highly uniform thermal oxides. Downstream, the wafer transitions directly to polysilicon gate electrode deposition within the 40nm BSI CMOS Image Sensor gate stack integration process flow. The interface state density (D_it), fixed oxide charge (Q_f), and thickness uniformity established during DGOX directly set the baseline for dark current, conversion gain, image lag, and readout timing across the entire 40nm BSI CMOS Image Sensor process flow.

Entry State and Sequence Logic

Upstream Dependencies

Prior to entering the DGOX module, the wafer has completed STI etching, trench oxide filling, chemical mechanical planarization (CMP), deep p-well formation, and threshold-adjust implants. During these steps, ion implantation introduces displacement damage into the near-surface silicon lattice. A sacrificial oxide layer present on the surface absorbs implant species but also accumulates heavy crystal damage, embedded impurities, and organic photoresist residues. Sacrificial oxidation integration principles mandate that this damaged surface oxide be removed completely before final gate oxide growth.

Module Process Topology

The sequence of operations within the DGOX module follows a precise hard-mask-based dual-oxidation integration scheme:

1. Sacrificial Oxidation (Step 69): A controlled thermal oxidation step grows a uniform SiO₂ layer to consume near-surface silicon defect sites.
2. SACOX Removal (Step 70): Dilute HF wet etching removes the sacrificial oxide, exposing an atomically clean crystalline silicon surface.
3. Thin Gate Oxide Growth (Step 71): High-quality thermal oxidation forms the baseline thin gate oxide across all active regions.
4. Nitride Hard Mask Deposition (Step 72): Chemical vapor deposition (CVD) coats the thin gate oxide with a protective Si₃N₄ hard mask.
5. Pre Litho Cleaning (Step 73): Surface preparation removes particulate and chemical contamination prior to photoresist coating.
6. Thick Gate Oxide - Photo (Step 74): Photolithography defines the pixel array regions where thicker gate oxide is required.
7. Nitride Hard Mask Etch (Step 75): Anisotropic/selective etching opens windows in the Si₃N₄ hard mask over the pixel area while leaving peripheral regions protected.
8. Ashing & Strip/Clean (Step 76): Oxygen plasma ashing and wet chemical cleans strip photoresist and organic residues.
9. Thick Gate Oxide Growth (Step 77): Thermal oxidation grows additional oxide in the unmasked pixel active areas, establishing the thicker gate dielectric profile.
10. Nitride Hard Mask Removal (Step 78): Selective wet etching removes the remaining Si₃N₄ hard mask from the peripheral thin oxide regions.

In this specific process topology, the thin gate oxide is grown first (Step 71) and protected by a nitride hard mask (Step 72), after which photolithography and hard mask etching expose the pixel areas (Steps 74–75) for subsequent thick gate oxide thermal growth (Step 77) prior to hard mask removal (Step 78).

Physical and Chemical Mechanisms

Sacrificial Oxide Removal and Surface Preparation

The removal of sacrificial oxide relies on wet etching using hydrofluoric acid (HF) solutions. HF reacts with silicon dioxide to break Si–O bonds and yield soluble hexafluorosilicic acid species:

SiO₂ + 6 HF -> H₂SiF₆ + 2 H₂O

Because wet etching is isotropic, the etch duration must be tightly controlled to prevent excessive undercutting of the isolation oxide at STI trench edges. Following oxide removal, standard RCA clean steps (SC1 and SC2) remove organic particles and trace metallic impurities. Metallic contaminants such as iron, copper, or nickel at the Si–SiO₂ interface form deep-level generation-recombination centers in the silicon bandgap, causing severe dark current spikes and white pixel defects in the final sensor.

Thermal Oxidation Kinetics and Hard Mask Protection

Thermal oxidation of silicon occurs via oxygen species diffusing through the growing dielectric matrix to react at the underlying Si–SiO₂ interface. According to the Deal-Grove model, oxidation kinetics start out linear and become parabolic as the oxidation proceeds [T1]. In the linear regime, oxidation is governed by the chemical reaction rate at the silicon surface; as the oxide layer thickens, the process transitions to the parabolic regime where oxidant diffusion through the existing film becomes rate-limiting.

During Step 77, the deposited Si₃N₄ hard mask acts as an impermeable diffusion barrier against molecular oxygen and water vapor. While thermal oxidation proceeds rapidly on the exposed silicon in the pixel active regions, the peripheral silicon beneath the nitride hard mask remains protected, maintaining its pre-established thin gate oxide thickness.

Interface Physics and MOS Band Bending

The electrostatics of both pixel and peripheral transistors are governed by the MOS band bending and threshold voltage relationships. The flat-band voltage V_fb represents the gate bias at which surface band bending is zero:

V_fb = ψ_g - ψ_s - Q_f / C_ox - Q_it / C_ox

where ψ_g is the gate electrode work function, ψ_s is the semiconductor work function, Q_f is fixed oxide charge, Q_it is interface trap charge, and C_ox is gate oxide capacitance per unit area. The total gate voltage balance is given by:

V_g - V_fb = φ_s + V_ox

where φ_s is the surface potential and V_ox is the voltage drop across the oxide.

In pixel transfer transistors, controlling Q_it and surface potential φ_s is paramount. Because the signal charge is away from the surface in buried-channel arrangements, it has the advantages of higher mobility, less charge loss due to interface traps, and higher fringing fields for charge transfer . Minimizing interface traps prevents carrier trapping during charge transfer from the PPD to the FD, suppressing image lag.

Interfaces and Failure Propagation

Topographic Transitions and Stress Concentrations

The boundary between thick gate oxide pixel areas and thin gate oxide peripheral logic areas creates a physical step in surface topography. If this oxide step is overly abrupt, subsequent deposition of conformal polysilicon can lead to localized stress concentration or thinning at the step edge. During anisotropic polysilicon gate etching, step topography can cause stringer formation or localized over-etching, increasing the risk of gate-to-substrate dielectric breakdown.

Dark Current and White Pixel Generation

Any degradation of the Si–SiO₂ interface within the photodiode or transfer gate boundary directly degrades sensor image quality. High interface trap density (D_it) accelerates thermal generation of electron-hole pairs under dark conditions. Generated electrons collected by the PPD accumulation well manifest as baseline dark current or dark current shot noise. Unusually high localized defect clusters produce bright white pixels that degrade dynamic range and low-light performance.

Gate Oxide Thickness Non-Uniformity and V_t Mismatch

Variations in thermal oxidation furnace temperature, gas flow dynamics, or wafer spacing cause cross-wafer gate oxide thickness non-uniformity. Because gate capacitance C_ox is inversely proportional to oxide thickness, thickness variations directly alter transistor threshold voltage V_t and transconductance g_m:

ΔV_t ≈ - (Q_dep / C_ox) (Δt_ox / t_ox)

In the pixel array, transfer gate V_t mismatch causes pixel-to-pixel variations in charge transfer efficiency, appearing as fixed-pattern noise (FPN). In peripheral circuits, thin oxide V_t variation introduces timing jitter and non-linearity in column analog-to-digital converters (ADCs).

Irreversibility in BSI Processing

Front-end gate oxide quality cannot be repaired during subsequent back-end or backside processing. After FEOL completion, the wafer undergoes multi-layer interconnect formation, wafer bonding ([40nm BSI CMOS Image Sensor sensor and logic wafer bonding process flow](/blog/40nm-bond-sensor-and-logic-wafer-bonding-process-flow)), backside silicon thinning, and optical filter integration. Any latent gate oxide defect, interface trap, or metallic impurity introduced during DGOX remains permanently embedded in the active device layers.

Walk the Real Module

To see how these principles operate in a concrete manufacturing sequence, explore Sacrificial Oxidation Step 69 in the interactive flow. This step marks the official commencement of the dual gate-oxide module following active region and isolation patterning.

The DGOX module interacts directly with the 40nm BSI CMOS Image Sensor pixel and peripheral NMOS integration process flow. The dual oxide thicknesses set the distinct channel electrostatics for pixel NMOS devices (which prioritize low dark current and complete charge transfer) and peripheral NMOS devices (which prioritize high speed and low parasitic capacitance).

Related Learning Paths

Engineers interested in mastering 40nm image sensor fabrication should examine these adjacent topics:

• Overall Process Architecture: Review the 40nm BSI CMOS Image Sensor process flow to contextualize DGOX between isolation/well modules and back-end metallization.
• Downstream Gate Electrode Patterning: Study the 40nm BSI CMOS Image Sensor gate stack integration process flow to analyze polysilicon deposition, gate lithography, spacer formation, and source/drain implants over dual oxide topographies.
• Device-Level Co-Optimization: Consult the 40nm BSI CMOS Image Sensor pixel and peripheral NMOS integration process flow for details on threshold engineering and channel transport in pixel versus peripheral transistors.

Future Outlook

As BSI image sensor technology scales beyond 40nm toward sub-micron pixel pitches, DGOX integration faces evolving technological requirements:

1. Sub-Nanometer Thickness Control: Shrinking pixel geometries demand ultra-tight thermal oxidation control to minimize threshold voltage dispersion across multi-megapixel arrays.
2. Hybrid Dielectric Stacks: Future nodes may implement hybrid gate stacks that retain thermal SiO₂ for pixel transfer gates to keep interface trap densities low, while introducing high-k dielectrics (e.g., HfO₂) and metal gates in peripheral logic to curb gate leakage at reduced supply voltages.
3. Proximity Gettering Compatibility: Reduced thermal budgets associated with advanced gettering techniques (such as carbon/hydrocarbon co-implantation) require DGOX oxidation steps to minimize thermal budget while still achieving dense, high-quality SiO₂ films.
4. 3D Stacked Architectures: Monolithic and hybrid wafer bonding allow logic readout circuits to be built on a separate wafer optimized for advanced logic nodes, potentially simplifying single-wafer DGOX processing while demanding new dielectric stability standards during inter-wafer thermal bonding.