14nm FinFET Dummy-Gate Silicon Etch Over Fins: Physical Mechanisms, Profile Control, and Module Integration

Function in the Complete Flow

In advanced multi-gate architecture integration, particularly within the 14nm gate template definition, the formation of functional transistor gate structures relies on a replacement metal gate (RMG) scheme [P2, A1]. Rather than depositing fragile high-k metal gate (HKMG) materials at the beginning of the front-end-of-line sequence, modern logic manufacturing employs sacrificial placeholders known as dummy gates [P2, A1]. The dummy-gate silicon etch over fins step serves as the definitive subtractive patterning operation that carves these temporary sacrificial gates out of a blanket amorphous silicon (a-Si) or polysilicon (poly-Si) layer [P1, A1].

The primary integration imperative of this process module is to translate two-dimensional photolithographic patterns into precise three-dimensional topographic structures that cross over narrow, vertical single-crystal silicon channels [P1, A2]. This step receives a substrate covered with protruding three-dimensional silicon fins and a planarized sacrificial silicon overburden [A1]. It must selectively etch away the unwanted silicon across dense and isolated fin regions while stopping with extreme selectivity on an underlying ultra-thin oxide protective layer [P1, A1].

[Hard Mask Patterning] 
       │
       ▼
[a-Si Gate Etch over Fin Tops]  ◄── (Crucial RMG Template Definition)
       │
       ▼
[Spacer & S/D Epitaxy Module]

By completing the dummy gate etch FinFET operation, the process hands off vertical, high-aspect-ratio silicon features that serve as structural rigid templates for subsequent processing [P2, A2]. These features anchor the positioning of dielectric gate sidewall spacers, direct the self-aligned ion implantation or epitaxial growth of source and drain raised regions, and define the exact volumetric cavity that will later be filled by work-function metals and low-resistance gate conductive cores during the RMG replacement phase [P2, A2]. Consequently, any structural distortion, critical dimension (CD) variation, or surface damage induced during this single etching step is permanently encoded into the transistor's physical gate length and channel geometry [P2]. Understanding this step within the broader 14nm FinFET process flow is essential for mastering advanced logic fabrication [P2].

Upstream Input State

Prior to executing the dummy gate etch, the wafer undergoes complex substrate preparation, fin active area definition, and sacrificial film deposition modules [A1]. The structural state inherited by this step exhibits severe three-dimensional topography and delicate material interfaces that constrain the dry etch process window [P1, P2].

+-------------------------------------------------------+
|                Patterned Hard Mask                    |
+-------------------------------------------------------+
|                                                       |
|       Sacrificial Amorphous Silicon (a-Si)            |
|                                                       |
|             +-------------+                           |
|             | Silicon Fin |                           |
|             | (Single-    |                           |
|  Isolation  |  Crystal)   |  Shallow Trench Isolation |
|    Oxide    |             |          (STI)            |
|-------------+-------------+---------------------------|
|                   Silicon Substrate                   |
+-------------------------------------------------------+

The upstream surface topology comprises the following structural components:

• Protruding Silicon Fins: Narrow, tall single-crystal silicon channels projecting vertically above shallow trench isolation (STI) planar oxide surfaces [A1]. These fins exhibit high aspect ratios and rounded or flat fin-top profiles defined by prior self-aligned double patterning or anisotropic shallow trench etching modules [P2, A1].
• Sacrificial Interface Layer: An ultra-thin dummy gate oxide (or sacrificial thermal/chemical oxide) that wraps continuously around the top surface and vertical sidewalls of the protruding silicon fins [P1, A1]. This layer acts as a chemical etch stop and protects the underlying channel silicon from energetic ion damage [P1].
• Sacrificial Gate Conductor: A conformal or chemical-mechanical planarized blanket layer of sacrificial amorphous silicon (a-Si) or poly-Si that completely fills the inter-fin gaps and covers the fin structures [P2, A1]. Amorphous silicon is frequently preferred over poly-Si due to its smooth grain-free film structure, which minimizes line-edge roughness (LER) during fine-line patterning (Engineering Practice).
• Hard Mask Stack: Single or multi-layered dielectric hard masks (such as silicon nitride overlying silicon oxide) situated atop the sacrificial silicon layer [A1]. These hard masks have been pre-patterned via advanced immersion photolithography or self-aligned spacer-assisted lithography combined with dry etching [A1].

The main physical challenge inherited from upstream processing lies in aspect-ratio-dependent topography [P2]. The sacrificial silicon film varies in effective thickness: it is thinner directly over the tops of protruding fins and significantly thicker within the deep trenches between adjacent fins and over STI field oxide regions [P1, P2]. The etch process must therefore clear substantial silicon depth along the vertical fin sidewalls without breaching the ultra-thin protective oxide over the exposed fin tops [P1]. To further explore how gate stack definition fits into overall module integration, refer to the detailed breakdown in the 14nm FinFET gate stack integration process flow [P2].

Physical and Chemical Mechanisms

The dummy gate etch in 14nm gate stack integration is executed using high-density plasma reactive ion etching (RIE), typically generated within inductively coupled plasma (ICP) or transformer coupled plasma systems [P1, T2]. Achieving vertical sidewalls, high selectivity to underlying oxides, and minimal profile distortion across 3D fins requires precise balance between chemical radical reactions and physical ion-assisted bombardment mechanisms [P1, T2].

Chemical Kinetics and Gas Chemistry

The primary gas chemistry for a-Si poly-Si etch applications utilizes halogenated species, predominantly hydrogen bromide and chlorine, combined with controlled additions of oxygen and fluorinated gases [P1].

1. Halogen Radical Dissociation: In the high-density plasma, electron impact dissociation breaks down HBr and Cl₂ molecules into reactive bromine and chlorine atomic radicals [P1]. These halogen radicals chemically adsorb onto the exposed silicon surface, weakening Si-Si covalent bonds and forming volatile etch byproducts such as silicon tetrabromide ($SiBr_4$) and silicon tetrachloride ($SiCl_4$) [P1, T2].
2. Passivation Kinetics: Oxygen radicals react with etching byproducts and silicon surfaces to deposit an ultra-thin, non-volatile silicon oxybromide ($SiO_xBr_y$) passivation film on vertical sidewalls [P1]. This passivation layer blocks isotropic radical etching on vertical surfaces, enforcing anisotropic, directionally constrained etch profiles [P1, T2].

Pulsed High-Density Plasma Mechanics

Conventional continuous-wave (CW) plasmas often struggle with trade-offs between physical ion sputtering damage and non-uniform radical loading across complex 3D fin features [P1]. Advanced 14nm processing heavily relies on pulsed high-density plasma technology, where source power, bias power, or both are synchronously time-modulated [P1].

Continuous Wave (CW) Plasma:
Power:  |=========================================|  (Constant Ion/Radical Flux)
        -> High risk of micro-loading & fin faceting

Pulsed Plasma Mode (Time-Modulated):
Power:  |=== OFF ===|=== ON ===|=== OFF ===|=== ON ===|
        -> Thermal cooling in OFF cycle reduces peak ion energy
        -> Allows neutral radical passivation to stabilize sidewalls

During the power-on pulse phase, high electron temperatures generate dense ions and reactive radicals, driving directional ion-assisted etching at the trench bottom [P1]. During the power-off pulse phase, electron temperature rapidly cools, causing high-energy ion fluxes to decay while lower-energy neutral radicals continue diffusing to feature sidewalls [P1]. This time-domain decoupling of ion energy from neutral radical density yields distinct mechanistic advantages:

• Suppression of Feature Distortion: Micro-loading and electron charging at feature bottoms are mitigated, preventing localized micro-trenching along fin corners [P1, P2].
• Control of Ion Energy Distribution: Pulsing narrows the ion energy distribution, permitting high chemical etch rates while keeping kinetic impact energies below the sputtering threshold of the underlying ultra-thin oxide layer [P1].
• Faceting Prevention: Lower effective ion energy during pulsed cycles prevents physical faceting of the top corners of the silicon fin [P1].

Selectivity and Endpoint Dynamics

The etch sequence is partitioned into distinct phase steps: a high-rate main etch that removes the bulk of the sacrificial silicon overburden, followed by a highly selective over-etch phase [T2, A1]. As the etch front reaches the top of the protective oxide layer over the fins, optical emission spectroscopy (OES) monitors chemical byproduct emission intensities (such as elemental silicon or silicon monoxide spectral lines) to detect the exact transition endpoint [T2].

Upon endpoint detection, the process switches to an over-etch chemistry enriched in HBr and oxygen [P1]. Bromine radicals exhibit exceptionally high chemical selectivity toward silicon compared to silicon dioxide because the silicon-oxygen bond energy is substantially higher than the silicon-silicon bond energy [T2]. This chemical barrier stops vertical etching on the ultra-thin fin oxide while continuing to clear residual silicon "stringers" along deep fin sidewall corners [P1, P2].

Substrate Energy State & Subthreshold Dependence:
I_{ds} \propto \exp\left(\frac{q V_{gs}}{\eta k T}\right)

Where $I_{ds}$ represents drain current, $V_{gs}$ is gate voltage, $q$ is electron charge, $k$ is Boltzmann's constant, $T$ is absolute temperature, and $\eta$ is the subthreshold slope factor [T1]. Maintaining clean structural profile definition during dummy gate etch prevents physical channel variations that would directly disrupt this exponential carrier transport behavior [T1].

Downstream Impact and Failure Propagation

Because the dummy gate structure establishes the physical spatial footprint for all subsequent front-end-of-line gate modules, profile deviations during this etch propagate directly into critical electrical and yield failures [P2, A2].

Etch Non-Ideality                Physical Defect                  Transistor Failure Mode
─────────────────                ───────────────                  ───────────────────────
Oxide Breakthrough  ───────────> Fin Recess / Faceting  ─────────> Vt Shift & SCE Leakage
Silicon Footing     ───────────> Gate-to-Gate Shorting  ─────────> Yield Loss & Resistance Spike
Profile Tapering    ───────────> Lg Non-Uniformity      ─────────> Subthreshold Swing Degradation
Hard Mask Erosion   ───────────> Severe LER / LWR       ─────────> Random Dopant & Vt Variability

1 [T2]. Ultra-Thin Oxide Breakthrough and Fin Erosion

If the over-etch chemistry exhibits insufficient selectivity or excess bias power, energetic ion bombardment breaks through the ultra-thin sacrificial oxide layer protecting the fin tops [P1, P2]. This leads to physical silicon erosion, fin recess, and top-corner faceting [P1, P2].

• Device Consequence: Recessing the silicon fin reduces the effective conductive channel height ($H_{fin}$), directly decreasing drive current ($I_{on}$) [T1]. Furthermore, sharp faceted corners amplify localized electric fields, degrading the subthreshold swing ($S$) as described by physical scaling relations:

  S = \eta \left( \frac{k T}{q} \right) \ln(10)
  

  Where degraded capacitive coupling increases $\eta$, exacerbating short-channel effects (SCE) and static off-state leakage current ($I_{off}$) [T1].

2. Sacrificial Silicon Residues (Footing and Stringers)

Incomplete etching within narrow inter-fin spaces leaves residual silicon "stringers" along the base of the fins or STI interfaces [P2].

• Integration Consequence: Unetched sacrificial silicon acts as a physical bridge between adjacent gate lines, resulting in catastrophic gate-to-gate short circuits [P2]. Additionally, silicon footing distorts the spatial region where dielectric inner spacers are formed, preventing clean epitaxy of source and drain regions [A2].

3. Sidewall Profile Non-Verticality (Tapering vs (Engineering Practice). Undercutting)

Inadequate control of the sidewall passivation film ($SiO_xBr_y$) alters the dummy gate angle [P1, T2].

• Tapered Profile: Excessive passivation yields a wide gate bottom, artificially increasing the effective gate length ($L_g$) near the base of the fin relative to the top [P2]. This increases parasitic outer fringe capacitance and reduces switching speed (Engineering Practice).
• Undercut Profile: Insufficient passivation allows lateral radical attack, undercutting the dummy gate underneath the hard mask cap [T2]. This leads to gate collapse, inconsistent physical gate length, and unmanageable threshold voltage variability across the wafer [P2].

4. Line-Edge Roughness (LER) Transfer

Erosion or striation of the overlying hard mask during the dummy-gate silicon etch over fins transfers micro-roughness directly into the sacrificial silicon sidewalls [A1, P2]. After replacement metal gate processing, this roughness translates into metal gate LER, inducing severe localized fluctuations in work function and threshold voltage [P2].

Walk the Real Step

To see how this specific operation fits into the complete interactive sequencing of advanced logic manufacturing, explore the detailed process node step:

Open GATE Step 91 in the interactive flow

In this process step, the primary operational focus is executing high-selectivity anisotropic removal of amorphous silicon over protruding fin topography while terminating cleanly on the protective dielectric interface [P1, A1]. Step 91 acts as the critical bridge separating hard mask definition from the spacer deposition and epitaxial source/drain modules, solidifying the spatial gate template required for true 14nm multi-gate logic performance [P2, A1].

Related Learning Paths

To gain a broader perspective on how dummy gate processing integrates with surrounding module sequences and downstream replacement integration, explore the following detailed integration guides:

• 14nm FinFET process flow: A comprehensive overview of the full integration module hierarchy, tracing the journey from initial bulk silicon fin patterning, shallow trench isolation, dummy gate definition, source/drain epitaxy, and replacement metal gate formation to back-end metallization layers [P2].
• 14nm FinFET gate stack integration process flow: A focused examination of the replacement metal gate module, detailing the removal of the sacrificial a-Si dummy gate, interface layer engineering, high-k dielectric atomic layer deposition, work-function metal layer tuning, and aluminum/tungsten fill metal planarization [P2].

Future Outlook

As device architectures scale beyond the 14nm FinFET generation into gate-all-around (GAA) nanosheet structures and complementary field-effect transistors (CFET), the dummy gate etch operation faces unprecedented structural challenges [P2, A2].

14nm FinFET Architecture               Sub-2nm GAA Nanosheet Architecture
┌───┐       ┌───┐                      ┌──────────────────────────────┐
│ G │       │ G │                      │     Dummy Gate Overburden    │
│ a │  Fin  │ a │                      ├──────────────────────────────┤
│ t │  ┌─┐  │ t │                      │  ===== Si Nanosheet =====    │
│ e │  │ │  │ e │                      │  ----- SiGe Sacrificial ---- │
└───┘  └─┘  └───┘                      │  ===== Si Nanosheet =====    │
──────────────────                      └──────────────────────────────┘
(Vertical Sidewall Etch)               (Complex Multi-Layer Cavity Etch)

In GAA nanosheet flows, the dummy gate etch must carve through sacrificial silicon surrounding alternating silicon and silicon-germanium ($Si/SiGe$) epitaxial superlattice stacks [A2]. Key evolution vectors include:

• Atomic Layer Etching (ALE): Transitioning from conventional continuous or pulsed plasma RIE toward quasi-atomic layer etching [P1]. Cyclic ALE processes utilize self-limiting adsorption of halogen species followed by low-energy ion exposure, achieving sub-nanometer profile control with absolute zero recess of underlying sacrificial channels (Engineering Practice).
• Isotropic vs. Anisotropic Synergies: Future GAA integration schemes require advanced dry etch techniques capable of transitioning seamlessly from highly anisotropic vertical gate cuts to ultra-selective isotropic lateral recessed etches to liberate nanosheet channels without inducing structural collapse [P2, A2].
• Material Selection: Beyond traditional amorphous silicon, next-generation dummy gate templates explore silicon-germanium alloys or dielectric sacrificial materials that offer ultra-high etch selectivity relative to un-doped channel sheets, minimizing channel degradation at sub-2nm nodes [P2, A2].