14nm FinFET Embedded Silicon Germanium Source-Drain Integration: Process Flow Principles and Strain Engineering Mechanisms

Role in the Complete Flow

In the 14nm FinFET technology node, the embedded silicon germanium (eSiGe) source-drain module serves as one of the most performance-critical integration sequences in the entire p-type field-effect transistor (pFET) fabrication flow [P1]. This module receives a partially constructed FinFET structure from upstream steps: the silicon fins have been patterned and shaped, the shallow trench isolation (STI) has been formed and recessed, the gate stack has been deposited and patterned, and the first spacer or offset spacer has been defined along the gate sidewalls [A1]. At this point, the source and drain regions of the pFET fins are still composed of bare silicon, and no intentional channel strain has been introduced through epitaxial means [A2].

The 14nm embedded silicon germanium source-drain integration must deliver three things downstream [P1]. First, it must selectively remove silicon from the pFET source/drain areas to create recessed cavities, then refill those cavities with epitaxially grown SiGe that is heavily doped with boron [P1]. Second, the SiGe epitaxy must introduce uniaxial compressive strain into the pFET channel, which enhances hole mobility and thereby increases drive current [P2]. Third, the elevated source/drain topography created by the epitaxial growth must provide a sufficient silicon-volume landing pad for subsequent silicidation and contact formation steps [A1].

The downstream consumers of this module include the second spacer formation, the silicide (self-aligned silicide, or salicide) module, and the contact module [T2]. If the eSiGe epitaxy is poor — whether due to insufficient strain transfer, excessive defect density, or inadequate doping activation — the consequences propagate directly into threshold voltage shifts, increased source/drain series resistance, degraded on-current, and elevated contact resistance [P2].

Entry State and Sequence Logic

Upstream Dependencies

The SD_ESIGE module process flow begins after several critical upstream modules have been completed (Engineering Practice). The 14nm FinFET sidewall spacer integration process flow has formed the initial offset spacer that defines the proximity of the source/drain cavity to the channel [A1]. The gate stack — typically a gate-last high-k/metal gate (HKMG) structure — has been patterned and protected (Engineering Practice). The fin geometry has been finalized through fin cut and fin recess steps [A2].

The entry state also includes the deposition of a spin-on hardmask material, commonly referred to as CSOH (carbon-doped spin-on hardmask), which serves as a sacrificial masking layer [A1]. The S/D SiGe CSOH Coat integration principles are rooted in the need to protect nFET regions while pFET source/drain processing proceeds [P2]. Because 14nm FinFET technology is a CMOS process, both nFET and pFET devices coexist on the same wafer, and selective processing of only pFET source/drain regions requires robust masking [P1].

Sequence Ordering Logic

The ordering of the SD_ESIGE module relative to adjacent modules is not arbitrary (Engineering Practice). The source/drain cavity etch must occur after spacer formation because the spacer defines the lateral boundary of the cavity, which in turn determines the strain transfer distance to the channel [A1]. If the cavity etch were performed before spacer formation, the strain-enhancement volume would be unconstrained and the junction placement would be uncontrolled [A1].

Similarly, SiGe epitaxy must occur before the second spacer and silicide modules [P1]. The epitaxial SiGe growth raises the source/drain topography above the original fin surface, and this elevated profile is essential for the silicide reaction to have sufficient silicon consumption volume [P1]. If silicide formation preceded epitaxy, the silicide-silicon interface would be destroyed during the high-temperature epitaxial prebake, leading to uncontrolled phase transformations [A1].

The CSOH coat and patterning sequence must be carefully ordered: the hardmask is applied, lithography defines the pFET source/drain regions, and the hardmask is etched to expose only the pFET source/drain silicon [A1]. After cavity etch and SiGe epitaxy, the CSOH is removed [A2]. This sequence ensures that nFET fins remain protected throughout the entire pFET source/drain processing window [A1].

Physical and Chemical Mechanisms

Strain Engineering Fundamentals

The fundamental physics underlying 14nm embedded silicon germanium source-drain integration is strain engineering [P3]. Silicon germanium has a larger lattice constant than pure silicon due to the larger atomic radius of germanium [P2]. When SiGe is epitaxially grown on a silicon substrate, the lattice mismatch generates compressive strain in the SiGe layer and, critically, transfers compressive stress laterally into the adjacent silicon channel region [P2].

According to band structure modulation theory, uniaxial compressive strain in the channel direction modifies the valence band structure of silicon [P3]. It lifts the degeneracy of the heavy-hole and light-hole bands, reduces the hole effective mass, and suppresses inter-valence-band scattering [P3]. The net effect is a significant enhancement of hole mobility in the pFET channel, which directly translates to higher drive current for a given gate overdrive [P2].

As transistor gate pitch shrinks from older nodes to 14nm, the source/drain stress volume available for strain generation decreases, causing channel strain from embedded SiGe to degrade [P3]. This geometric constraint is a key reason why the 14nm node requires careful optimization of the SiGe epitaxy process, cavity geometry, and germanium concentration to maintain strain effectiveness within a shrinking footprint [P1].

Selective Epitaxial Growth Chemistry

The SiGe epitaxy in this module relies on selective epitaxial growth (SEG), which exploits differences in chemical reactivity between exposed silicon surfaces and dielectric surfaces [P1]. The epitaxial deposition is typically performed using chemical vapor deposition (CVD) with precursors such as dichlorosilane (SiH2Cl2) and germane (GeH4) [P1]. Hydrogen chloride (HCl) is introduced as an etchant gas that suppresses nucleation on non-silicon surfaces such as silicon oxide and silicon nitride [T2].

The mechanism of selectivity is kinetic: on exposed silicon, the adsorption and surface migration rates of silicon and germanium species dominate over the etching rate, resulting in net deposition [P1]. On dielectric surfaces, the etching rate of HCl exceeds the nucleation rate, preventing polycrystalline deposition [T2]. This selectivity is essential because the source/drain regions are surrounded by spacers, STI, and gate structures — all of which must remain free of unwanted SiGe deposition [P2].

In Situ Prebake and Native Oxide Removal

Prior to epitaxial growth, the exposed silicon source/drain surfaces must be free of native oxide and other contaminants [A1]. An in situ high-temperature prebake in a hydrogen ambient is performed to thermally desorb the native silicon dioxide (SiO2) layer [T2]. This step is critical because even a sub-nanometer residual oxide layer would block epitaxial alignment and generate defects at the SiGe-silicon interface [P2].

However, the prebake thermal budget must be carefully controlled (Engineering Practice). Excessive thermal exposure can cause deformation of the silicon fin structure, particularly at the fin top and sidewalls, which are mechanically delicate at 14nm dimensions [A1]. The prebake temperature window is therefore bounded on the lower side by the need for complete oxide removal and on the upper side by the requirement to preserve fin geometric integrity [A1].

In Situ Boron Doping

During SiGe epitaxy, boron is incorporated in situ using a boron-containing precursor such as diborane (B2H6) [P1]. The boron doping serves a dual purpose: it provides the p-type dopant source for the source/drain junction, and it contributes to strain engineering because boron has a smaller atomic radius than silicon, partially compensating the lattice expansion from germanium [P2]. The interplay between germanium content, boron concentration, and growth temperature jointly determines the strain level, crystal quality, and source/drain sheet resistance [P2].

CSOH Masking Mechanism

The spin-on hardmask, or CSOH, functions as a polymeric carbon-rich dielectric that is spin-coated onto the wafer surface and then cured (Engineering Practice). Its role in the SD_ESIGE module is to serve as a pattern-transfer and protection layer during the pFET source/drain cavity etch [P2]. The carbon content provides etch resistance against fluorocarbon-based reactive ion etching (RIE) chemistries used for silicon recess etching [P1]. The spin-on nature of the material enables conformal coverage over the three-dimensional fin and gate topography, which is critical at 14nm where aspect ratios are significant [A1].

Interfaces and Failure Propagation

Spacer–Cavity Interface

The interface between the spacer sidewall and the source/drain cavity is a critical boundary (Engineering Practice). The spacer defines how close the SiGe epitaxy can approach the channel [P2]. If the spacer is too thin, the cavity etch may encroach laterally toward the channel, causing junction leakage and threshold voltage shifts [A1]. If the spacer is too thick, the strain transfer distance increases and the compressive stress reaching the channel diminishes [P2].

The cavity etch profile itself — whether it is sigma-shaped, rectangular, or tapered — directly affects strain coupling efficiency [P3]. A sigma-shaped cavity, which exposes specific crystallographic facets, can amplify stress transfer through facet-dependent epitaxial growth dynamics [P2]. However, achieving a consistent sigma profile across all pFET devices on a wafer requires precise etch chemistry and endpoint control [P1].

SiGe–Silicon Heterointerface

The epitaxial SiGe-silicon interface is where lattice mismatch manifests most directly [P2]. If the germanium concentration is too high, the mismatch strain exceeds the critical thickness for coherent epitaxy, and misfit dislocations nucleate at the interface [P2]. These dislocations serve as both scattering centers that degrade carrier mobility and as leakage paths that increase junction off-state current [P2]. There is therefore an optimal germanium concentration window that balances strain enhancement against defect generation [P2].

If the prebake is insufficient and residual native oxide remains, the epitaxial growth initiates on a contaminated surface, producing polycrystalline or highly defective SiGe [P1]. This degrades both strain transfer and doping activation, and it can also cause voids or delamination at the interface [T2].

CSOH–Epitaxy Interface

The CSOH hardmask must be completely removed before subsequent processing (Engineering Practice). Residual organic contamination from incomplete CSOH stripping can poison the SiGe surface, leading to poor silicide formation in downstream modules [P2]. Conversely, if the CSOH removal process is too aggressive, it may damage the exposed SiGe surface or etch the epitaxial material non-uniformly, altering the source/drain topography [P2].

Downstream Failure Propagation

Failures in the eSiGe module propagate directionally into multiple downstream modules (Engineering Practice). Poor strain transfer reduces pFET drive current, which manifests as failed speed-bin specifications [P3]. Excessive defect density at the SiGe-silicon interface increases junction leakage, which elevates off-state power [P2]. Inadequate boron doping activation increases source/drain series resistance, which degrades both on-current and contact resistance [T2]. Insufficient source/drain elevation reduces the silicide reaction volume, potentially causing incomplete salicidation or silicide agglomeration [P2].

These failure modes are particularly insidious because they may not be detectable at the module level alone; they often only manifest in final electrical test, making root-cause diagnosis difficult without extensive failure analysis (Engineering Practice).

Walk the Real Module

To explore the step-by-step sequence of the 14nm FinFET embedded silicon germanium source-drain integration process flow in detail, you can follow the interactive module walkthrough [P1]. The complete SD_ESIGE module process flow includes CSOH coat, lithography, hardmask etch, pFET source/drain cavity recess, pre-epitaxy cleaning, selective SiGe epitaxy with in situ boron doping, and hardmask removal [P1].

Each step in this sequence has specific integration dependencies and failure-mode considerations (Engineering Practice). For a hands-on exploration of how these steps connect, Open SD_ESIGE Step 99 in the interactive flow (Engineering Practice). This interactive resource allows you to trace the module sequence and understand how each step's output becomes the next step's entry condition (Engineering Practice).

The broader context of this module within the complete 14nm fabrication sequence can be understood through the 14nm FinFET process flow overview, which explains how the eSiGe module fits among the dozens of other modules that together constitute the full technology flow [P1]. For comparison, the nFET counterpart — the 14nm FinFET epitaxial silicon source-drain integration process flow — uses similar selective epitaxial growth principles but with different strain objectives and dopant species [P1].

Related Learning Paths

Engineers studying the 14nm FinFET eSiGe module should explore several adjacent topics to build a complete understanding:

Strain Engineering Evolution: The transition from planar to FinFET architecture changed how strain is introduced and maintained [P3]. In planar devices, biaxial strain from SiGe virtual substrates could enhance both electron and hole mobility [P2]. In FinFETs, the three-dimensional geometry and free surfaces during source/drain epitaxy constrain strain transfer, making uniaxial strain from embedded source/drain the dominant mechanism [P3]. Understanding this evolution provides context for why eSiGe integration becomes progressively more challenging at advanced nodes (Engineering Practice).

Selective Epitaxy Fundamentals: The SEG process is shared between pFET eSiGe and nFET epitaxial silicon-carbon (Si:C) source/drain modules [P1]. Although Si:C has not been successfully implemented in FinFETs due to unconstrained free surfaces during growth, the underlying principles of surface-selective deposition and etch-back are common [P1].

Spacer Module Integration: The spacer module directly controls the source/drain cavity geometry and junction placement [A1]. Engineers should study how spacer width, height, and material composition interact with cavity etch profiles and SiGe epitaxy uniformity [P2].

Contact Resistance Engineering: The eSiGe module's in situ boron doping sets the baseline for contact resistance [T2]. As devices scale, the Schottky barrier height at the silicide-silicon interface becomes a dominant component of source/drain series resistance, and the SiGe valence band modulation helps reduce this barrier [P2].

Future Outlook

As the semiconductor industry moves beyond 14nm toward 7nm and 5nm nodes, several trends are reshaping the embedded source/dain strain landscape [P3]. First, the diminishing source/drain stress volume at tighter gate pitches is reducing the effectiveness of embedded SiGe strain transfer [P2]. Research is exploring higher germanium content alloys and alternative channel materials such as SiGe channels or germanium channels that carry intrinsic strain, decoupling strain generation from the source/drain epitaxy module [P2].

Second, the transition from FinFET to gate-all-around (GAA) nanosheet architectures fundamentally changes source/drain integration [A2]. In GAA devices, the source/drain epitaxy must wrap around released nanosheet channels, creating new challenges for selective growth uniformity and strain transfer efficiency [P2].

Third, the role of the CSOH hardmask and other sacrificial masking layers is evolving (Engineering Practice). Advanced nodes are exploring multi-layer hardmask stacks and self-aligned patterning techniques that reduce reliance on conventional spin-on materials, driven by the need for tighter dimensional control and lower defect levels [P3].

Finally, in situ doping techniques are being extended to include alternative dopant species and multi-layer epitaxial structures that combine strain, doping, and contact interface engineering in a single growth sequence [T2]. These developments promise to maintain the performance gains that embedded SiGe source/drain integration has delivered since its adoption at the 90nm node, even as the geometric constraints of advanced nodes become increasingly severe [P2].