What is the 40nm BSI CMOS Image Sensor process flow?

The 40nm BSI (Backside Illuminated) CMOS Image Sensor process flow is a specialized semiconductor manufacturing sequence for high-performance image sensors. Unlike traditional front-side illuminated (FSI) architecture, BSI places the photodiode beneath the metal interconnect layers and receives light from the wafer backside, dramatically improving quantum efficiency and low-light performance. This flow contains 417 process steps and is entirely free to access.

What is the difference between BSI and FSI image sensors?

In FSI architecture, incident light must pass through the metal interconnect layers to reach the photodiode — metal lines block and reflect some light, reducing quantum efficiency. BSI flips the wafer so light enters directly from the backside into the photodiode, bypassing the metal stack. This gives BSI sensors significantly higher sensitivity at the same pixel size, making them ideal for smartphone cameras and low-light applications.

What is the role of Deep Trench Isolation (DTI) in the 40nm CIS flow?

Deep Trench Isolation (DTI) creates physical and optical barriers between adjacent pixel photodiodes in BSI CIS. The trenches are filled with low-refractive-index material, preventing photo-generated carriers from diffusing into neighboring pixels (electrical crosstalk) and blocking oblique light from crossing pixel boundaries (optical crosstalk). This is critical for maintaining image quality as pixel pitch shrinks.

What is the role of Color Filter Array (CFA) and microlens in CIS?

The Color Filter Array sits above each pixel, arranging red, green, and blue filters in a Bayer pattern (RGGB) so each pixel captures only one color. The microlens array sits above the CFA, focusing incident light onto each pixel's active area to improve light collection efficiency. In BSI architecture, the shorter optical path and absence of metal obstruction simplify CFA and microlens alignment and increase the fill factor.

What are the key modules in the 40nm CIS process flow?

Key modules include: STI (Shallow Trench Isolation), Well formation, Gate, PD (Photodiode formation), F-DTI (Frontside Deep Trench Isolation), PMD/Contact, multi-level metal interconnect (MET0-MET6), DBI (Direct Bond Interconnect — wafer bonding), backside thinning (THIN), backside passivation (BKPAS), LS Grid (Light Shield Grid), CFA (Color Filter Array), microlens (UOCL), and Bondpad. The flow spans 42 modules and 417 process steps.

40nm BSI CMOS Image Sensor - 40nm Process Flow | SemiFlows

40nm BSI CMOS Image SensorFree after sign-in

40nm28nm 14nm 7nm

CIS/ISP Wafer Bond Align

290/ 417

CIS/ISP Wafer TC Bond

Post-Bond Anneal

286CIS/ISP wafer bond pairing 287RF surface activation CIS 288RF surface activation ISP 289CIS/ISP Wafer Bond Align 290CIS/ISP Wafer TC Bond 291Post-Bond Anneal

Process Cross-Section

Loading visual…

Step highlight

Thermocompression promotes contact and joining of aligned CIS/ISP interfaces for subsequent annealing and backside thinning; mechanical strength and electrical continuity require separate assessment (Engineering Practice).