14nm FinFETPreview

c, which stabilizes the gate profile prior to subsequent wet etching and atomic-layer-based recess processes [P3]. This step exists because a purely wet-based poly removal at this stage would exhibit strong pattern-density dependence and lateral undercut, degrading gate CD control in the three-dimensional FinFET geometry, as cautioned for high‑aspect‑ratio poly features in FinFET integration [P2]. By leaving a residual poly thickness through a dry, anisotropic mechanism, the process creates a well-defined vertical reference surface that improves uniformity and predictability of the following POP Poly Wet Etch step [P3]. The partial dry etch also reduces the total wet etch burden, which is critical for minimizing silicon fin loss and gate dielectric disturbance that are known risks during aggressive over‑etching and cleaning sequences [P1]. Unlike PMD Partial Etch Back or Metal Resistor Etch Stop Partial Etch, which primarily modulate dielectric or metal thickness for planarization or electrical isolation purposes, POP Poly Partial Dry Etch directly conditions the dummy gate conductor geometry that defines the effective gate length in the RMG module [P3]. In contrast to the earlier Poly Open SiN Hardmask Etch, which focuses on selective removal of a dielectric hardmask, this step targets polysilicon itself and therefore directly influences the subsequent replacement metal gate cavity geometry [A1]. Its distinction from the later POP Poly Wet Etch lies in its anisotropic, plasma‑driven nature, which is used here specifically to pre-shape the poly profile and suppress wet-etch-induced variability [P3].

Physical and Chemical Mechanisms

The POP Poly Partial Dry Etch operates through a plasma-assisted etching mechanism in which energetic ions provide directional momentum transfer while chemically reactive species form volatile silicon-containing byproducts at the surface, enabling anisotropic polysilicon removal [P3]. Ion bombardment lowers the effective activation energy for surface reactions by breaking Si–Si bonds and enhancing adsorption of reactive radicals, a principle consistent with ion‑enhanced interfacial reaction models used to explain plasma oxidation and etching phenomena [P1]. Because the gate dielectric beneath the dummy poly is extremely thin, the process must carefully balance chemical reactivity and ion energy to avoid oxygen‑assisted plasma oxidation of the underlying silicon or gate dielectric, which can later manifest as apparent silicon recess after wet cleaning [P1]. From a device physics perspective, maintaining precise control of the remaining dummy poly height is essential because it ultimately defines the depth and shape of the replacement metal gate trench, which in turn affects gate electrostatics and threshold voltage uniformity in FinFETs [T1]. Variations in poly removal translate into variations in effective gate length and gate capacitance, both of which directly impact short‑channel control and subthreshold behavior as described by MOS electrostatic scaling theory [T1]. Therefore, this dry partial etch is intentionally terminated before full poly clearance to decouple profile definition from the more aggressive, less directional wet etch that follows [P3].

Material, Method Selection, and Parameter Interaction

A dry plasma etch is selected over a wet method at this stage because plasma processes inherently offer superior directionality and pattern transfer fidelity in high‑aspect‑ratio FinFET gate structures, where isotropic chemical etching would lead to uncontrolled lateral loss [P2]. Polysilicon is particularly suitable for plasma etching due to its ability to form volatile halogenated reaction products, enabling efficient chemical removal when assisted by ion bombardment [P3]. The interaction between ion energy and chemical radical flux governs the etch anisotropy: increasing ion contribution enhances verticality but simultaneously raises the risk of dielectric damage and plasma oxidation, while increasing purely chemical activity improves selectivity but promotes lateral etching [P1]. Process monitoring principles for this step rely on indirect thickness or endpoint control rather than complete clearance detection, because the intent is partial, not total, removal of poly, a control philosophy consistent with model‑based and run‑to‑run control concepts developed for polysilicon gate etching [P3]. Uniformity across the wafer is particularly sensitive to plasma density distribution and feature‑scale loading effects, which can modulate local etch rates and therefore the remaining poly thickness [P3]. The residual poly left by this step intentionally acts as a buffer layer, protecting the gate dielectric and silicon fin during the subsequent wet etch and atomic‑layer etch recess operations [P1].

Node-Specific Considerations for 14 nm FinFET

At the 14 nm FinFET node, the three‑dimensional gate wrapping around narrow fins significantly amplifies the electrical sensitivity to gate length and profile variations, making partial poly shaping steps like this one more critical than in planar technologies [T1]. As reviewed in FinFET scaling literature, over‑etch damage and fin silicon loss become increasingly severe as dimensions shrink, necessitating tighter partitioning of dry and wet etch responsibilities in the gate module [P2]. The POP Poly Partial Dry Etch reflects this node‑specific integration strategy by using a controlled plasma step to pre‑define geometry while deferring final clearance to more selective, lower‑damage processes that follow [P3].