14nm FinFETPreview

OL dielectric build-up [P1]. This placement is critical because the preceding spacer etch-back steps intentionally expose multiple materials and sharp three-dimensional topographies that would otherwise be vulnerable to plasma and wet-etch damage during subsequent contact patterning and dielectric deposition [A1]. By forming a continuous silicon nitride liner at this stage, the process establishes a well-defined etch boundary and mechanical barrier that preserves fin geometry and spacer integrity through the remainder of the MOL flow [P1]. From an integration perspective, this CESL prepares the surface for the subsequent POP oxide liner deposition by providing a chemically stable and etch-selective interface that suppresses uncontrolled oxide consumption and intermixing during liner formation [P3]. The nitride layer also mitigates moisture uptake and defect generation in the flowable SOG PMD fill that follows, thereby stabilizing gap-fill behavior and downstream CMP uniformity [P2]. In this sense, the CESL ALD SiN step is not a passive liner but an active integration enabler that conditions both the mechanical and chemical boundary conditions for the PMD stack [P1].

Physical and Chemical Deposition Mechanism

CESL ALD SiN deposition operates through plasma-enhanced atomic layer deposition, in which silicon-containing precursors and nitrogen plasma exposures are alternated to drive self-limiting surface reactions on all accessible surfaces [P1]. During the precursor half-cycle, organo-aminosilane molecules chemisorb onto reactive surface sites until saturation is reached, which inherently decouples film growth from local feature geometry and enables conformality in high-aspect-ratio FinFET structures [P3]. The subsequent plasma half-cycle generates reactive nitrogen radicals that abstract organic ligands, promote Si–N bond formation, and densify the growing network, completing one atomic-scale growth increment [P4]. The plasma enhancement is essential because it supplies non-thermal energy that lowers reaction activation barriers, allowing complete nitridation and ligand removal at temperatures compatible with MOL thermal budgets [P1]. When implemented in a remote or low-damage configuration, radical diffusion rather than ion bombardment dominates surface activation, which minimizes lattice damage and charge trapping in the fin channel and gate-adjacent regions [P1]. This balance between chemical reactivity and physical gentleness underpins the ability of ALD SiN to function as an electrically benign yet chemically robust CESL in scaled FinFETs [T1].

Material and Method Selection Logic

Silicon nitride is selected as the CESL material because its strong Si–N bonding network provides high etch selectivity relative to oxides, low permeability to hydrogen and oxygen, and sufficient mechanical stiffness to act as an effective barrier during aggressive contact etches [P1]. Compared with PECVD nitride, ALD-deposited SiN offers superior conformality and thickness control, which are mandatory for coating fin sidewalls and spacer corners without pinch-off or thinning [P3]. These attributes directly translate into tighter etch-stop margins and reduced variability in contact critical dimensions [A2]. Process parameters interact primarily through surface chemistry saturation and plasma-assisted conversion efficiency rather than through gas-phase transport, which distinguishes ALD from CVD-based CESL approaches [P4]. Increasing plasma reactivity enhances ligand removal and film density but simultaneously raises the risk of ion-induced damage if radical-to-ion ratios are not properly managed [P1]. Similarly, precursor reactivity and surface residence time influence both conformality and impurity incorporation, establishing a trade-off space that must be optimized to achieve dense, low-defect SiN without compromising fin or spacer integrity [P3].

Node-Specific Considerations for 14 nm FinFETs

At the 14 nm FinFET node, fin heights and pitches create moderate-to-high aspect-ratio features that already exceed the reliable conformality limits of conventional PECVD liners, making ALD a practical necessity rather than an optimization choice [T2]. Additionally, device performance at this node remains sensitive to stress transfer and interface defectivity, so the CESL must provide mechanical protection without introducing uncontrolled strain or trap states near the channel [P2]. The adoption of ALD SiN CESL at 14 nm therefore reflects a node-specific convergence of geometric scaling, thermal budget constraints, and reliability requirements that collectively favor plasma-enhanced ALD over legacy deposition methods [P1].