What is the 7nm FinFET semiconductor process flow?

The 7nm FinFET process flow represents one of the most advanced semiconductor manufacturing nodes using immersion lithography (without EUV). It combines aggressive fin pitch scaling, self-aligned quadruple patterning (SAQP), advanced strain engineering, and cobalt-based contacts to achieve significant density and performance improvements over 14nm and 10nm nodes.

How many process steps are in the 7nm FinFET flow?

The 7nm FinFET process flow on SemiFlows contains 714 detailed process steps, making it the most comprehensive flow on the platform. It covers the complete integration from wafer preparation through 12+ metal layers. Note: metal layers M4-M8 share an identical process sequence and are represented as a single template layer.

What patterning technology is used at 7nm?

The 7nm node primarily uses Self-Aligned Quadruple Patterning (SAQP) for critical layers like fins, combined with Litho-Etch-Litho-Etch (LELE) for other tight-pitch layers. SAQP extends immersion lithography to achieve sub-40nm pitches without requiring EUV lithography, though at the cost of increased process complexity and more patterning steps.

What are the key innovations in 7nm vs 14nm process technology?

Key innovations at 7nm include: tighter fin pitch via SAQP (vs SADP at 14nm), cobalt contacts and local interconnects replacing tungsten for lower resistance, more aggressive gate length scaling, advanced epitaxial source/drain profiles, and 12+ metal interconnect layers with copper dual-damascene and advanced barrier metals.

What is the role of cobalt in 7nm semiconductor manufacturing?

Cobalt plays a critical role at 7nm as a replacement for tungsten in middle-of-line contacts (MOL). As contact dimensions shrink, tungsten's high resistivity barrier liner consumes too much of the contact volume. Cobalt offers lower bulk resistivity and thinner barriers, significantly reducing contact resistance. It is used in trench contacts (CB/CA) and via-to-contact connections (VC).

7nm FinFET - 7nm Process Flow | SemiFlows

7nm FinFETPreview

40nm 28nm 14nm7nm

Metal Gate CMP

305/ 714

Gate Contact_E1 Lithography

Gate Contact_E2 Lithography

305Gate Contact_E1 Lithography 314Gate Contact_E2 Lithography 319Gate Contact Integrated Etch

+109 steps

Process Cross-Section

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Step highlight

Gate-contact resist pattern definition: distinguish the immediate change from later electrical outcomes (Engineering Practice).

In depth

This step follows the CSOH/SiON stack and pre-lithography clean, defines the gate-contact E1 resist pattern, and hands it to subsequent SiON etching. The existing replacement metal gate is the eventual contact target. Lithography here neither penetrates the hard mask or dielectric nor creates a conducting connection.