14nm FinFETPreview

eas through masking or kinetic selectivity [A1]. This step establishes a robust dielectric buffer that electrically isolates the silicon channel from subsequent dummy gate materials, preparing a controlled interface for the gate-first replacement sequence that follows, consistent with the need for high-quality Si/SiO2 interfaces emphasized in scaled MOS structures [T1]. By performing this oxidation before dummy gate amorphous silicon deposition, the process ensures that the dummy gate rests on a chemically stable and mechanically uniform oxide, reducing variability during CMP and refill steps [P2]. The placement of this step prior to dummy gate formation is critical because oxide quality and thickness directly influence gate capacitance uniformity and interface state density, which in turn affect threshold voltage control in FinFETs as described for multi-gate devices [T1]. This step is distinct from later thick oxide gate or fin etch operations in the flow because it is an additive, thermally driven oxidation process rather than a subtractive patterning step [A2]. While thick oxide gate/fin etch removes oxide to define geometry, selective thick gate oxidation intentionally grows oxide to engineer electrical isolation and surface chemistry at a precise integration point [P4]. The selectivity is achieved through material-dependent oxidation kinetics and masking, allowing oxidation only where silicon is exposed, following the fundamental principle that thermal oxidation proceeds only on silicon surfaces [T1].

Physical and Chemical Mechanisms

The core physical mechanism of selective thick gate oxidation is the thermal oxidation of silicon, where oxygen-containing species diffuse to the silicon surface and react to form SiO2, consuming silicon in the process [T1]. This reaction is governed by diffusion through the growing oxide and interface reaction kinetics, leading to a self-limiting growth behavior that inherently smooths surface damage left by prior etch steps, as also exploited for fin sidewall smoothing in FinFET fabrication [P3]. Because oxidation proceeds normal to the silicon surface, it naturally conforms to the three-dimensional fin geometry, providing uniform coverage on fin tops and sidewalls, which is essential for tri-gate electrostatic symmetry [T1]. From a device-physics perspective, the grown oxide reduces interface trap density by replacing damaged silicon bonds with stable Si–O bonds, thereby lowering interface state density and improving electrostatic control, consistent with the reliability improvements observed when thermally grown interfacial layers are used in HKMG FinFETs [P2]. The thicker oxide regions also locally reduce gate-to-channel coupling, which can be used to manage electric field crowding and suppress leakage paths such as gate-induced drain leakage, a concern highlighted in scaled MOSFETs [T1].

Material and Method Selection Logic

Thermal oxidation is selected over deposited dielectrics because it produces the highest-quality Si/SiO2 interface achievable in silicon technology, a fact repeatedly emphasized in MOSFET scaling literature [T1]. In contrast to chemically grown or deposited oxides, thermally grown oxide is denser and has fewer residual defects, which directly translates into improved reliability and reduced bias-temperature instability, as experimentally demonstrated in FinFET gate stacks [P2]. The method also leverages the inherent selectivity of oxidation to silicon, avoiding parasitic growth on adjacent dielectric or nitride regions and simplifying integration [P2]. Process parameters interact directionally through temperature, ambient chemistry, and time, which together control oxidation rate, oxide density, and interfacial quality without requiring explicit thickness targeting [P2]. Increasing thermal energy accelerates oxidant diffusion and interface reaction, while oxidizing ambient composition influences the chemical potential driving oxide formation, consistent with the oxidation kinetics framework discussed in MOS physics texts [T1]. These directional interactions allow engineers to balance oxide robustness against thermal budget constraints that are critical for preserving fin geometry and previously defined features (Engineering Practice).

Node-Specific Considerations for 14 nm FinFETs

At the 14 nm node, FinFET electrostatics are highly sensitive to interface quality because the channel is fully depleted and body doping is no longer an effective knob for threshold voltage control [P1]. As a result, any interface defects or thickness non-uniformity introduced at this stage would directly translate into threshold voltage variability and mobility degradation, making selective thick gate oxidation particularly critical for this technology generation [T1]. The three-dimensional fin geometry further amplifies the importance of conformal oxidation, as sidewall channel mobility and roughness effects are known to strongly impact overall drive current in FinFETs [P3]. The step therefore serves as a reliability and variability control module tailored to 14 nm integration, rather than a simple geometric oxide formation [P2]. Its role is to reset surface chemistry after aggressive fin and SAC oxide etches, establishing a stable baseline for subsequent dummy gate processing and ultimately for high-k/metal gate replacement, in line with the integration logic seen in advanced FinFET process flows [P2].