14nm FinFET

Device Context and Integration Logic

The As-Si Hard Mask Etch step exists to selectively transfer the fin-patterning geometry into the amorphous silicon hard mask layer that ultimately defines fin critical dimensions and placement for the 14 nm FinFET architecture [A1].In the FIN_PATTERN module, this step is positioned after lithographic definition and before the sequential SiO2 and SiN hard mask etches so that the lateral fidelity of the fin image is first established in a material with h…

• [High] Critical Dimension Bias and Variability: Non-ideal balance between chemical etching and ion directionality can cause lateral CD loss or gain in the As-Si hard mask, which then propagates through subsequent oxide and nitride hard mask etches and directly alters fin width, impacting electrostatic control and threshold voltage variability [T1].- [High] Line-Edge and Sidewall Roughness Transfer: Micro-masking or stochastic ion damage during As-Si etching can generate rough sidewalls…